Reset Flags Register (Pmc_Rst); Temperature Control And Status Register (Pmc_Tpctrlstat) - NXP Semiconductors MC9S08SU16 Reference Manual

14.7.2 Reset Flags Register (PMC_RST)

Address: 1850h base + 1h offset = 1851h
Bit 7
Read 0
Write
Reset
0
POR 0
LVR 0
* Notes:
• u = Unaffected by reset.
Field
7 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
6 Power-on Reset Flag
PORF
This bit is set to 1 when a power-on reset (POR) occurs. This flag can only be cleared by writing a 1.
Writing a 0 takes no effect.
0 POR does not occur.
1 POR occurs.
5 Low Voltage Reset (LVR) Flag
LVRF
This bit is set to 1 when a low voltage reset occurs in the full performance mode (FPM). This flag can only
be cleared by writing a 1. Writing a 0 takes no effect.
0 Low voltage reset does not occur.
1 Low voltage reset occurs.
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.

14.7.3 Temperature Control and Status Register (PMC_TPCTRLSTAT)

Address: 1850h base + 2h offset = 1852h
Bit 7
Read
Write
Reset
0
NXP Semiconductors
6 5
PORF LVRF
u* u*
1 1
1 1
PMC_RST field descriptions
6 5
0
SWON
0 0
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 14 Power Management Controller (PMC)
4 3
0 0
0 0
0 0
Description
4 3
HTDS
TEMPEN
0 0
2 1
0
0 0
0 0
0 0
2 1
HTIE HTIF
0 0
0
0
0
0
0
0
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