Cnvh:l Registers - NXP Semiconductors MC9S08SU16 Reference Manual

19.5.8.2 CnVH:L registers

If (CLKS[1:0] = 0:0), then CnVH:L registers are updated when their second byte is
written.
If (CLKS[1:0] ≠ 0:0), then CnVH:L registers are updated according to the selected mode:
• If the selected mode is output compare mode, then CnVH:L registers are updated
after their second byte is written and on the next change of the FTM counter.
• If the selected mode is EPWM mode, the CnVH:L registers are updated after both
bytes have been written and the FTM counter changes from MODH:L to all zeroes.
If the FTM counter is a free running counter, then this update is made when the FTM
counter changes from 0xFFFF to 0x0000.
• If the selected mode is CPWM mode, then CnVH:L registers are updated after both
bytes have been written and the FTM counter changes from MODH:L to (MODH:L
– 0x0001).
19.5.9 BDM mode
When BDM mode is active, the FlexTimer counter and the channels output are frozen.
However, the value of FlexTimer counter or the channels output are modified in BDM
mode when:
• A write of any value to the CNTH or CNTL registers
counter to the value of 0x0000 and the channels output to their initial value, except
for channels in output compare mode.
19.6 Reset overview
The FTM is reset whenever any chip reset occurs.
When the FTM exits from reset:
• The FTM counter and the prescaler counter are zero and are stopped (CLKS[1:0] =
0b00)
• The timer overflow interrupt is zero
• The channels interrupts are zero
NXP Semiconductors
(Timer overflow
(Channel (n)
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 19 FlexTimer Module (FTM)
(Counter reset) resets the FTM
interrupt)
interrupt)
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