Crc Data Register: High 0 (Crc_Dh0) - NXP Semiconductors MC9S08SU16 Reference Manual

Memory map and register descriptions
When final data written, the CRC result can be read from this data register. In 16-bit CRC
mode, the CRC result is avaiable in DL1:DL0. In 32-bit CRC mode, all registers are
used. Reads to this register at any time returns the intermediate CRC value, provided
CRC module is configured.
Address: 1890h base + 0h offset = 1890h
Bit 7
Read
Write
Reset
1
Field
DH1 CRC Data Bits 31:24

16.3.2 CRC Data register: High 0 (CRC_DH0)

This section describes the function of CRC data registers (DH1:DH0:DL1:DL0). The set
of CRC data registers contains the value of seed, data, and checksum. When
CTRL[WAS] is set, any write to the data registers will be regarded as seed for CRC
module. When CTRL[WAS] is de-asserted, any write to the data registers will be
regarded as data for CRC module for general CRC computation.
When programming the seed value in 16-bit CRC mode, the DH1:DH0 are not used and
reads to these registers returns an indeterminate value. For 32-bit CRC, all registers are
used.
When programming data values for CRC calculation, data must be provided in DL0
register only. Writes to other bytes of data regsiters are ignored.
When final data written, the CRC result can be read from this data register. In 16-bit CRC
mode, the CRC result is avaiable in DL1:DL0. In 32-bit CRC mode, all registers are
used. Reads to this register at any time returns the intermediate CRC value, provided
CRC module is configured.
Address: 1890h base + 1h offset = 1891h
Bit 7
Read
Write
Reset
1
Field
DH0 CRC Data Bits 23:16
246
6 5
1 1
CRC_DH1 field descriptions
6 5
1 1
CRC_DH0 field descriptions
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
4 3
DH1
1 1
Description
4 3
DH0
1 1
Description
2 1
1 1
2 1
1 1
NXP Semiconductors
0
1
0
1