Pwm Fault Control Register: High (Pwm_Fctrlh) - NXP Semiconductors MC9S08SU16 Reference Manual

Memory Map and Register Descriptions

26.4.4 PWM Fault Control Register: High (PWM_FCTRLH)

Address: 40h base + 3h offset = 43h
Bit 7
Read
Write
Reset
0
Field
7–4 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
FPOL FAULTn Polarity Control
These read/write bits control the polarity of the FAULTn pin inputs. A reset clears FPOLn. FPOL2 is also
used to control the polarity of the external sync input and output.
0 A 1 on FAULTn indicates a fault condition
1 A 0 on FAULTn indicates a fault condition
26.4.5 PWM Fault Status Acknowledge Register: Low
(PWM_FLTACKL)
After enabling clock to PWM, but before enabling any PWM
interrupt, clear all flags in FLTACK.
Address: 40h base + 4h offset = 44h
Bit 7
Read 0
Write
Reset
0
Field
7 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
6 FAULT3 Pin Acknowledge
FTACK3
510
6 5
0
0 0
PWM_FCTRLH field descriptions
NOTE
6 5
0
FTACK3
0 0
PWM_FLTACKL field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
4 3
0 0
Description
4 3
0
FTACK2
0 0
Description
2 1
FPOL
0 0
2 1
0
FTACK1
0 0
NXP Semiconductors
0
0
0
FTACK0
0