Table of Contents
Advertisement
Chapter 14 Power Management Controller (PMC)
In the FPM mode, when LVR reset occurs, the flag bit PMC_RST[LVRF] is set to 1. The
flag LVRF is also set to 1 when a POR occurs, but is not affected by other system resets.
14.8.3.1 LVR in low power mode
The LVR circuit is disabled when PMC enters the reduced performance mode (RPM).
14.8.4 Low voltage warning (LVW)
The LVW circuit monitors the 5 V VREG
outputs (VDDX/VDDA) and the
VDDX
VREG
output (VREFH). The LVW circuit can generate an interrupt when
VREFH
detecting a low voltage condition on VDDX/VDDA or VREFH.
14.8.4.1 LVW on VDDX/VDDA
Low voltage on VDDX/VDDA sets the flag bit PMC_LVCTLSTAT1[SLVWF] to 1.
When PMC_LVCTLSTAT1[SLVWIE] is set, the low voltage condition incurs an
interrupt.
To clear the SLVWF flag, user should write 1 to PMC_LVCTLSTAT1[SLVWACK].
14.8.4.2 LVW on VREFH
Low voltage on VREFH sets the flag PMC_LVCTLSTAT2[RLVWF] to 1. When
PMC_LVCTLSTAT2[RLVWIE] is set, the low voltage condition incurs an interrupt.
To clear the RLVWF flag, user should write 1 to PMC_LVCTLSTAT2[RLVWACK].
The VREFH low voltage level can be configured through the LVWCFG[1:0] bits in
PMC_VREFHLVW register.
14.8.4.3 LVW in low power mode
The LVW circuit is disabled when PMC enters the reduced performance mode (RPM).
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
NXP Semiconductors
231
Advertisement
Table of Contents
