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Manuals and User Guides for NXP Semiconductors MC9S08LG32. We have 1 NXP Semiconductors MC9S08LG32 manual available for free PDF download: Reference Manual

NXP Semiconductors MC9S08LG32 Reference Manual

NXP Semiconductors MC9S08LG32 Reference Manual (373 pages)

Brand: NXP Semiconductors | Category: Microcontrollers | Size: 6 MB

Table of Contents

Table of Contents
7
Chapter 1 Device Overview
21
Chapter 2 Pins and Connections
27
- Pins and Connections
  27
- Introduction
  27
- Device Pin Assignment
  27
- Recommended System Connections
  31
- Power
  33
- Oscillator
  33
- Reset
  34
- Background / Mode Select (BKGD/MS)
  34
- Irq
  35
- LCD Pins
  35
- General-Purpose I/O (GPIO) and Peripheral Ports
  36
Chapter 3 Modes of Operation
41
- Modes of Operation
  41
- Introduction
  41
- Features
  41
- Run Mode
  41
- Active Background Mode
  41
- Wait Mode
  42
- Stop Modes
  43
- Stop2 Mode
  43
- Stop3 Mode
  44
- Active BDM Enabled in Stop Mode
  45
- LVD Enabled in Stop Mode
  45
- Mode Selection
  45
- On-Chip Peripheral Modules in Stop Modes
  48
Chapter 4 Memory
49
- MC9S08LG32 Series Memory Map
  49
- Reset and Interrupt Vector Assignments
  50
- Register Addresses and Bit Assignments
  52
- Reserved Flash Locations
  59
- Ram
  60
- Flash
  60
- Features
  61
- Program and Erase Times
  61
- Program and Erase Command Execution
  62
- Burst Program Execution
  63
- Access Errors
  65
- Flash Block Protection
  65
- Vector Redirection
  66
- Security
  66
- Flash Registers and Control Bits
  67
- Flash Clock Divider Register (FCDIV)
  68
- Flash Options Register (FOPT and NVOPT)
  69
- Flash Configuration Register (FCNFG)
  70
- Flash Protection Register (FPROT and NVPROT)
  70
- Flash Status Register (FSTAT)
  71
- Flash Command Register (FCMD)
  72
Chapter 5 Resets, Interrupts, and General System Control
73
Chapter 6 Parallel Input/Output Control
97
- Parallel Input/Output Control
  97
- Introduction
  97
- Pins Shared with LCD
  97
- Port Data and Data Direction
  97
- Pullup, Slew Rate, and Drive Strength
  98
- Port Internal Pullup Enable
  98
- Port Slew Rate Enable
  99
- Port Drive Strength Select
  99
- Open Drain Operation
  99
- Pin Behavior in Stop Modes
  99
- Parallel I/O and Pin Control Registers
  100
- Port a Registers
  100
- Port B Registers
  104
- Port C Registers
  107
- Port D Registers
  110
- Port E Registers
  113
- Port F Registers
  116
- Port G Registers
  119
- Port H Registers
  122
- Port I Registers
  125
Chapter 7 Keyboard Interrupt (S08KBIV2)
128
- Keyboard Interrupt (S08KBIV2)
  128
- Introduction
  128
- Module Configuration
  128
- KBI Clock Gating
  128
- Features
  130
- Modes of Operation
  130
- Block Diagram
  130
- External Signal Description
  131
- Register Definition
  131
- KBI Status and Control Register (KBISC)
  131
- KBI Pin Enable Register (KBIPE)
  132
- KBI Edge Select Register (KBIES)
  132
- Functional Description
  133
- Edge Only Sensitivity
  133
- Edge and Level Sensitivity
  133
- KBI Pullup/Pulldown Resistors
  134
- KBI Initialization
  134
Chapter 8 Central Processor Unit (S08CPUV5)
135
- Central Processor Unit (S08CPUV5)
  135
- Introduction
  135
- Features
  135
- Programmer's Model and CPU Registers
  136
- Accumulator (A)
  136
- Index Register (H:X)
  136
- Stack Pointer (SP)
  137
- Program Counter (PC)
  137
- Condition Code Register (CCR)
  137
- Addressing Modes
  139
- Inherent Addressing Mode (INH)
  139
- Relative Addressing Mode (REL)
  139
- Immediate Addressing Mode (IMM)
  139
- Direct Addressing Mode (DIR)
  139
- Extended Addressing Mode (EXT)
  140
- Indexed Addressing Mode
  140
- Special Operations
  141
- Reset Sequence
  141
- Interrupt Sequence
  141
- Wait Mode Operation
  142
- Stop Mode Operation
  142
- BGND Instruction
  143
- HCS08 Instruction Set Summary
  144
Chapter 9 LCD Module (S08LCDLPV1)
158
- LCD Module (S08LCDLPV1)
  158
- Introduction
  158
- LCD Clock Sources
  158
- LCD Modes of Operation
  158
- LCD Status after Stop2 Wakeup
  158
- LCD Clock Gating
  158
- Features
  160
- Modes of Operation
  161
- Block Diagram
  161
- External Signal Description
  162
- Lcd[44:0]
  163
- Cap1 Cap2
  163
- Ll3
  163
- Register Definition
  163
- LCD Control Register 0 (LCDC0)
  163
- LCD Control Register 1 (LCDC1)
  164
- LCD Voltage Supply Register (LCDSUPPLY)
  165
- LCD Regulated Voltage Control Register (LCDRVC)
  166
- LCD Blink Control Register (LCDBCTL)
  167
- LCD Status Register (LCDS)
  168
- LCD Pin Enable Registers 0-5 (LCDPEN0-LCDPEN5)
  168
- Backplane Enable Registers 0-5 (BPEN0-BPEN5)
  169
- LCD Waveform Registers (LCDWF[44:0])
  170
- Functional Description
  174
- LCD Driver Description
  175
- LCDWF Registers
  183
- LCD Display Modes
  183
- LCD Charge Pump, Voltage Divider, and Power Supply Operation
  185
- Resets
  188
- Interrupts
  189
- Initialization Section
  189
- Initialization Sequence
  189
- Initialization Examples
  190
- Application Information
  194
- LCD Seven Segment Example Description
  195
- LCD Contrast Control
  198
- Stop Mode Recovery
  199
Chapter 10 Analog-To-Digital Converter (S08ADC12V1)
200
- Analog-To-Digital Converter (S08ADC12V1)
  200
- Introduction
  200
- ADC Shared with LCD
  200
- ADC Reference and Supply Voltage
  200
- ADC Clock Gating
  200
- Module Configurations
  201
- Features
  204
- ADC Module Block Diagram
  204
- External Signal Description
  205
- Analog Power
  206
- Dda
  206
- Ssa )
  206
- Voltage Reference High
  206
- Refh )
  206
- Voltage Reference Low
  206
- Refl )
  206
- Analog Channel Inputs (Adx)
  206
- Register Definition
  206
- Status and Control Register 1 (ADCSC1)
  206
- Status and Control Register 2 (ADCSC2)
  208
- Data Result High Register (ADCRH)
  208
- Data Result Low Register (ADCRL)
  209
- Compare Value High Register (ADCCVH)
  209
- Compare Value Low Register (ADCCVL)
  210
- Configuration Register (ADCCFG)
  210
- Pin Control 1 Register (APCTL1)
  211
- Pin Control 2 Register (APCTL2)
  212
- 10Pin Control 3 Register (APCTL3)
  213
- Functional Description
  214
- Clock Select and Divide Control
  215
- Input Select and Pin Control
  215
- Hardware Trigger
  215
- Conversion Control
  215
- Automatic Compare Function
  218
- MCU Wait Mode Operation
  218
- MCU Stop3 Mode Operation
  219
- MCU Stop2 Mode Operation
  219
- Initialization Information
  220
- ADC Module Initialization Example
  220
- Application Information
  222
- External Pins and Routing
  222
- Sources of Error
  223
Chapter 11 Internal Clock Source (S08ICSV3)
226
- Internal Clock Source (S08ICSV3)
  226
- Introduction
  226
- Features
  228
- Block Diagram
  228
- Modes of Operation
  229
- External Signal Description
  230
- Register Definition
  230
- ICS Control Register 1 (ICSC1)
  231
- ICS Control Register 2 (ICSC2)
  233
- ICS Trim Register (ICSTRM)
  233
- ICS Status and Control (ICSSC)
  234
- Functional Description
  236
- Operational Modes
  236
- Mode Switching
  238
- Bus Frequency Divider
  239
- Low Power Bit Usage
  239
- DCO Maximum Frequency with 32.768 Khz Oscillator
  239
- Internal Reference Clock
  239
- External Reference Clock
  240
- Fixed Frequency Clock
  240
- Local Clock
  240
Chapter 12 Inter-Integrated Circuit (S08IICV2)
241
- Inter-Integrated Circuit (S08IICV2)
  241
- Introduction
  241
- Module Configuration
  241
- IIC Clock Gating
  241
- Features
  243
- Modes of Operation
  243
- Block Diagram
  243
- External Signal Description
  244
- SCL - Serial Clock Line
  244
- SDA - Serial Data Line
  244
- Register Definition
  244
- IIC Address Register (Iicxa)
  245
- IIC Frequency Divider Register (Iicxf)
  245
- IIC Control Register (Iicxc1)
  248
- IIC Status Register (Iicxs)
  248
- IIC Data I/O Register (IICXD)
  249
- IIC Control Register 2 (Iicxc2)
  250
- Functional Description
  251
- IIC Protocol
  251
- 10-Bit Address
  254
- General Call Address
  255
- Resets
  255
- Interrupts
  255
- Byte Transfer Interrupt
  255
- Address Detect Interrupt
  256
- Arbitration Lost Interrupt
  256
- Initialization/Application Information
  257
Chapter 13 Serial Communications Interface (S08SCIV4)
259
- Serial Communications Interface (S08SCIV4)
  259
- Introduction
  259
- Module Instances
  259
- Module Configuration
  259
- SCI Clock Gating
  259
- Features
  261
- Modes of Operation
  261
- Block Diagram
  262
- Register Definition
  264
- SCI Baud Rate Registers (Scixbdh, Scixbdl)
  264
- SCI Control Register 1 (Scixc1)
  265
- SCI Control Register 2 (Scixc2)
  266
- SCI Status Register 1 (Scixs1)
  267
- SCI Status Register 2 (Scixs2)
  269
- SCI Control Register 3 (Scixc3)
  270
- SCI Data Register (Scixd)
  271
- Functional Description
  271
- Baud Rate Generation
  271
- Transmitter Functional Description
  272
- Receiver Functional Description
  273
- Interrupts and Status Flags
  275
- Additional SCI Functions
  276
Chapter 14 Serial Peripheral Interface (S08SPIV4)
278
- Serial Peripheral Interface (S08SPIV4)
  278
- Introduction
  278
- Module Configuration
  278
- SPI Clock Gating
  278
- Features
  280
- Block Diagrams
  280
- SPI Baud Rate Generation
  282
- External Signal Description
  283
- SPSCK - SPI Serial Clock
  283
- MOSI - Master Data Out, Slave Data in
  283
- MISO - Master Data In, Slave Data out
  283
- SS - Slave Select
  283
- Modes of Operation
  284
- SPI in Stop Modes
  284
- Register Definition
  284
- SPI Control Register 1 (Spixc1)
  284
- SPI Control Register 2 (Spixc2)
  285
- SPI Baud Rate Register (Spixbr)
  286
- SPI Status Register (Spixs)
  287
- SPI Data Register (Spixd)
  288
- Functional Description
  289
- Master Mode
  289
- Slave Mode
  290
- SPI Clock Formats
  291
- Special Features
  293
- SPI Interrupts
  295
- Mode Fault Detection
  295
Chapter 15 Real-Time Counter (S08RTCV1)
297
- Real-Time Counter (S08RTCV1)
  297
- Introduction
  297
- RTC Clock Gating
  297
- Features
  299
- Modes of Operation
  299
- Block Diagram
  300
- External Signal Description
  300
- Register Definition
  300
- RTC Status and Control Register (RTCSC)
  301
- RTC Counter Register (RTCCNT)
  302
- RTC Modulo Register (RTCMOD)
  302
- Functional Description
  302
- RTC Operation Example
  303
- Initialization/Application Information
  304
Chapter 16 Timer/Pulse-Width Modulator (S08TPMV3)
306
- Timer/Pulse-Width Modulator (S08TPMV3)
  306
- Introduction
  306
- TPM External Clock
  306
- Module Instances
  306
- Module Configuration
  306
- TPM Clock Gating
  307
- Features
  308
- Modes of Operation
  308
- Block Diagram
  309
- Signal Description
  311
- Detailed Signal Descriptions
  311
- Register Definition
  314
- TPM Status and Control Register (Tpmxsc)
  314
- TPM-Counter Registers (Tpmxcnth:tpmxcntl)
  315
- TPM Counter Modulo Registers (Tpmxmodh:tpmxmodl)
  316
- TPM Channel N Status and Control Register (Tpmxcnsc)
  317
- TPM Channel Value Registers (Tpmxcnvh:tpmxcnvl)
  318
- Functional Description
  319
- Counter
  320
- Channel Mode Selection
  321
- Reset Overview
  324
- General
  324
- Description of Reset Operation
  324
- Interrupts
  324
- Description of Interrupt Operation
  325
Chapter 17 Modulo Timer (S08MTIMV1)
327
- Modulo Timer (S08MTIMV1)
  327
- Introduction
  327
- MTIM Clock Gating
  327
- Features
  329
- Modes of Operation
  329
- Block Diagram
  330
- External Signal Description
  330
- Memory Map and Register Definition
  331
- Memory Map (Register Summary)
  331
- Register Descriptions
  331
- Functional Description
  335
- MTIM Operation Example
  336
Chapter 18 Development Support
337
- Development Support
  337
- Introduction
  337
- Forcing Active Background
  337
- Module Configuration
  337
- Features
  338
- Background Debug Controller (BDC)
  338
- BKGD Pin Description
  339
- Communication Details
  339
- BDC Commands
  343
- BDC Hardware Breakpoint
  345
- Register Definition
  345
- BDC Registers and Control Bits
  346
- System Background Debug Force Reset Register (SBDFR)
  348
Chapter 19 Debug Module (DBG) (64K)
350
- Debug Module (DBG) (64K)
  350
- Introduction
  350
- Features
  350
- Modes of Operation
  351
- Block Diagram
  351
- Signal Description
  352
- Memory Map and Registers
  352
- Module Memory Map
  352
- Register Descriptions
  354
- Functional Description
  365
- Comparator
  365
- Breakpoints
  365
- Trigger Selection
  366
- Trigger Break Control (TBC)
  366
- Fifo
  370
- Interrupt Priority
  371
- Resets
  371
- Interrupts
  371

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