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System options
This will prevent accidental changes if the application program gets lost. The write to
SRS that services (clears) the COP counter must not be placed in an interrupt service
routine (ISR) because the ISR could continue to be executed periodically even if the main
application program fails.
If the bus clock source is selected, the COP counter does not increment while the MCU is
in background debug mode or while the system is in stop mode. The COP counter
resumes when the MCU exits background debug mode or stop mode.
If the 20 kHz LPO, ICSIRCLK, or CLK_IN clock source is selected, the COP counter is
re-initialized to zero upon entry to either background debug mode or stop mode and
begins from zero upon exit from background debug mode or stop mode.
Control bits
SOPT1[COPCLKS]
N/A
00/10
00/10
00/10
01
01
01
11
11
11
1. Windowed COP operation requires the user to clear the COP timer in the last 25% of the selected timeout period. This
column displays the minimum number of clock counts required before the COP timer can be reset when in windowed COP
mode (SOPT1[COPW] = 1).
9.6
System options
9.6.1 BKGD pin
After POR, PTB7/CLKOUT/BKGD/MS pin functions as BKGD output. Other functions
are selected by SIM_MUXPTBH[MUXPTB7]. This pin is an output only when
configured as PTB7.
100
Table 9-1. Configuration option
Clock source
SOPT1[COPT]
00
01
20 kHz LPOCLK /
ICSIRCLK
10
20 kHz LPOCLK /
ICSIRCLK
11
20 kHz LPOCLK /
ICSIRCLK
01
10
11
01
10
11
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
COP window opens
N/A
BUSCLK
6,144 cycles
BUSCLK
49,152 cycles
BUSCLK
196,608 cycles
CLK_IN
CLK_IN
CLK_IN
1
COP overflow count
N/A
COP is disabled
5
N/A
2
cycles
8
N/A
2
cycles
10
N/A
2
cycles
13
2
cycles
16
2
cycles
18
2
cycles
13
N/A
2
cycles
16
N/A
2
cycles
18
N/A
2
cycles
NXP Semiconductors
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