NXP Semiconductors MC9S12ZVMB-Family Reference Manual

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MC9S12ZVMB-Family

Reference Manual

S12 MagniV

Microcontrollers

Rev. 1.3

07 MAR 2017

MC9S12ZVMBRM

nxp.com

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Summary of Contents for NXP Semiconductors MC9S12ZVMB-Family

Page 1 MC9S12ZVMB-Family Reference Manual S12 MagniV Microcontrollers Rev. 1.3 07 MAR 2017 MC9S12ZVMBRM nxp.com...
Page 2 The MC9S12ZVMB-Family is targeted for safety relevant systems and has been developed using an ISO26262 compliant development system under the NXP Safe Assure program. For details of device usage in safety relevant systems refer to the MC9S12ZVMB Safety Manual. The document revision on the Internet is the most current. To verify this is the latest revision, refer to: nxp.com...
Page 3: Table Of Contents
Features ..............18 1.2.1 MC9S12ZVMB-Family member comparison ....... . . 18 1.2.2 ADC module versions .
Page 4 2.5.2 SCI Baud Rate Detection ..........112 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 5 4.5.3 Wake Up from Stop or Wait Mode ........141 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 6 6.4.4 State Sequence Control ..........206 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 7 Functional Description ............273 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 8 Use Cases and Application Information ..........350 9.9.1 List Usage — CSL single buffer mode and RVL single buffer mode ....350 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 9 11.6.1 Channel [3:0] Interrupt (C[3:0]F) ......... 386 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 10 13.1 Introduction ..............459 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 11 14.5.5 Recovery from Stop Mode ..........515 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 12 16.4 Functional Description ............552 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 13 18.3.1 Register Summary ........... . . 580 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 14 19.6 Initialization ..............667 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 15 H.2 Dynamic Electrical Characteristics ..........714 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 16 L.20 0x09C0-0x09C7 HSDRV0 ............754 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 17: Introduction
(12 V) components. The MC9S12ZVMB-Family is a new member of the S12 MagniV product line based on the enhanced performance, linear address space S12Z core and delivers an optimized solution with the integration of several key system components into a single device, optimizing system architecture and achieving significant space savings.
Page 18: Features
This section describes the key features of the MC9S12ZVMB-Family. 1.2.1 MC9S12ZVMB-Family member comparison Table 1-2 provides a summary of feature set differences within the MC9S12ZVMB-Family. All other features are common to all family members. Table 1-2. MC9S12ZVMB-Family devices Feature S12ZVMBA...
Page 19: Adc Module Versions
Chapter 1 Device Overview MC9S12ZVMB-Family 1.2.2 ADC module versions This device family features ADC V3. The ADC module description includes a superset of features for V1, V2 and V3. It also summarizes these minor version differences. 1.2.3 S12ZVMBA versions The FET-Predriver on the S12ZVMB version cannot be driven directly from the PMF PWM channels at a frequency of greater than 1KHz.
Page 20: Module Features
Chapter 1 Device Overview MC9S12ZVMB-Family • Autonomous periodic interrupt (API) • Two High-side Driver outputs • Three High Voltage Input (HVI) pins • One 20mA high-current output for use as Hall sensor supply • Supply voltage sensor with low battery warning •...
Page 21: Embedded Memory
Chapter 1 Device Overview MC9S12ZVMB-Family — Each comparator can be configured to monitor PC addresses or addresses of data accesses — Each comparator can select either read or write access cycles — Comparator matches can force state sequencer state transitions •...
Page 22: Clocks, Reset & Power Management Unit (Cpmu)
Chapter 1 Device Overview MC9S12ZVMB-Family 1.4.2.4 SRAM • Up to 4 Kbytes of general-purpose RAM with ECC — Single bit error correction and double bit error detection 1.4.3 Clocks, reset & power management unit (CPMU) • Real time interrupt (RTI) •...
Page 23: External Oscillator (Xosclcp)
Chapter 1 Device Overview MC9S12ZVMB-Family 1.4.4 External oscillator (XOSCLCP) • Amplitude controlled Pierce oscillator using 4 MHz to 20 MHz crystal — Current gain control on amplitude output — Signal with low harmonic distortion — Low power — Good noise immunity —...
Page 24: Serial Communication Interface Module (Sci)
Chapter 1 Device Overview MC9S12ZVMB-Family — 10.4 kBit/s — 20 kBit/s — Fast Mode (up to 250 kBit/s) • Selectable pull-up of 34 k or 330 k (in Shutdown Mode, 330 k only) • Current limitation for LIN Bus pin falling edge.
Page 25: Supply Voltage Sensor (Bats)
Chapter 1 Device Overview MC9S12ZVMB-Family • ADC directly writes results to RAM, preventing stall of further conversions • Internal signals monitored by the ADC module — VRH, VRL, (VRL+VRH)/2 — Vsup monitor — VREG Vbg, and Temperature Sensor — Delta VBE Temperature Sensor —...
Page 26: High Side Driver
Chapter 1 Device Overview MC9S12ZVMB-Family • Diagnostic failure management • Integrated OP-amp functionality 1.4.15 High side driver • Selectable gate control: HSDR[HSDRx] register bits or PWM or timer channels • Open-load detection • Slew rate control • Over-current shutdown, comprising of: —...
Page 27: Block Diagram
Chapter 1 Device Overview MC9S12ZVMB-Family Block diagram Flash with ECC GDU-AMP AMPP0 AMPM0 48 K or 64 K bytes AMP0 VDDA EEPROM with ECC VSSA Current Sense Circuit PAD[8:0]/KWAD[8:0] 512 bytes AN[8:0] RAM with ECC 4 K bytes VRH_[2:0] 10-bit...
Page 28: Device Memory Map
Chapter 1 Device Overview MC9S12ZVMB-Family Device memory map Table 1-3 shows the device register memory map. All modules that can be instantiated more than once on S12 devices are listed with an index number, even if they are only instantiated once on this device family.
Page 29 Reserved register space shown above is not allocated to any module. This register space is reserved for future use. Writing to these locations has no effect. Read access to these locations returns zero. Table 1-4. MC9S12ZVMB-Family memory address ranges Size Device...
Page 30 6 KByte 0x1F_C000 NVM IFR 256 Byte 0x20_0000 Unmapped 6 MByte 0x80_0000 Unmapped address range Program NVM Low address aligned max. 128 KByte High address aligned 0xFF_FFFF Figure 1-2. MC9S12ZVMB-Family global memory map. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 31: Part Id Assignments
Chapter 1 Device Overview MC9S12ZVMB-Family 1.6.1 Part ID assignments The part ID is located in four 8-bit registers at addresses 0x0000-0x0003. The read-only value is a unique part ID for each revision of the chip. Table 1-5 shows the assigned part ID number and mask set number.
Page 32 Chapter 1 Device Overview MC9S12ZVMB-Family 1.7.2.1 RESET — External reset signal The RESET signal is an active low bidirectional control signal. It acts as an input to initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset. The RESET pin has an internal pull-up device.
Page 33 Chapter 1 Device Overview MC9S12ZVMB-Family 1.7.2.9 AN0_[11:0] — ADC input signals These are the analog inputs of the Analog-to-Digital Converter. ADC0 has up to 9 analog input channels connected to PAD[8:0] port pins. The channels AN_[11:9] are connected to HVI[2:0] respectively.
Page 34 Chapter 1 Device Overview MC9S12ZVMB-Family 1.7.2.14 Timer IOC1_[3:0] signals The signals IOC1_[3:0] are associated with the input capture or output compare functionality of the timer (TIM1) module. 1.7.2.15 PWM[5:4] signals The signals PWM[5:4] are associated with the PMF module digital channel outputs.
Page 35 Chapter 1 Device Overview MC9S12ZVMB-Family 1.7.2.19.2 DBGEEV — External event input This signal is the DBG external event input. It is input only. Within the DBG module, it allows an external event to force a state sequencer transition A falling edge at the external event signal constitutes an event.
Page 36 Chapter 1 Device Overview MC9S12ZVMB-Family 1.7.2.23.3 GHG[1:0] - High-side gate signals These pins are the gate drives for the high-side power FETs. The drivers provide a high current with low impedance to turn on and off the high-side power FETs.
Page 37: Power Supply Pins
Chapter 1 Device Overview MC9S12ZVMB-Family 1.7.2.23.13 AMP0 - Current sense amplifier output This is the current sense amplifier output. 1.7.3 Power supply pins The power and ground pins are described below. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible.
Page 38 Chapter 1 Device Overview MC9S12ZVMB-Family 1.7.3.7 EVDD This is a high current, low voltage drop output intended for supplying external devices in a range of up to 20mA. Configuring the pin direction as output automatically enables the high current capability. It includes an over current protection feature.
Page 39: Package And Pinouts
64LQFP The pin outs are shown in the following diagrams. The signal to pin mapping is specified in Table 1-7 Pins specified as N.C. have no physical connection to silicon. Figure 1-3. MC9S12ZVMB-Family 48-pin LQFP pin out GLS1 VSUP GLG1...
Page 40 Chapter 1 Device Overview MC9S12ZVMB-Family VSUP VLS_OUT VSSX1 GLS1 MC9S12ZVMB GLG1 N.C. 64-pin LQFP VSSX4 VBS1 GHG1 GHS1 N.C. GHS0 GHG0 VSSX2 VBS0 VSSX3 VSUPHS GLG0 N.C. Figure 1-4. MC9S12ZVMB-Family 64-pin LQFP pin out MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 41: Pin And Signal Mapping Overview
Chapter 1 Device Overview MC9S12ZVMB-Family 1.7.5 Pin and signal mapping overview Please refer to the PIM chapter for priority and routing information. Table 1-7. Pin summary (Sheet 1 of 3) LQFP Internal Pull Function Option Resistor Power Domai Rese CTRL Func.
Page 42 Chapter 1 Device Overview MC9S12ZVMB-Family Table 1-7. Pin summary (Sheet 2 of 3) LQFP Internal Pull Function Option Resistor Power Domai Rese CTRL Func. Func. Func. Func. Func. Func. State — PAD5 KWAD5 AN0_5 — — — — PERADL/ PPSADL...
Page 43 Chapter 1 Device Overview MC9S12ZVMB-Family Table 1-7. Pin summary (Sheet 3 of 3) LQFP Internal Pull Function Option Resistor Power Domai Rese CTRL Func. Func. Func. Func. Func. Func. State — IOC1_2 — — — — — PERT/ PPST —...
Page 44: Internal Signal Mapping
Chapter 1 Device Overview MC9S12ZVMB-Family Internal signal mapping This section specifies the mapping of inter-module signals at device level. 1.8.1 ADC connectivity 1.8.1.1 ADC reference voltages VRH_[2:1] are always mapped to VDDA, VRH_0 is mapped to VDDA in the 48LQFP package option but mapped to a dedicated VRH_0 pin in the 64LQFP package option.
Page 45: Gdu Timer Connectivity
Chapter 1 Device Overview MC9S12ZVMB-Family 1.8.2 GDU timer connectivity TIM1 IC3 can be mapped to the GDU using PIM (see the PIM specification) in order to measure the t delon times. tdeloff 1.8.3 PTU connectivity PTU reload_is_async is unused and forced to an inactive state at device level.
Page 46: Bdc Clock Source Connectivity
Chapter 1 Device Overview MC9S12ZVMB-Family Table 1-10. Control loop interface connectivity Device Level Event ADC0 trigger_0 PTUT0 Trigger (MUX Option) 1. PMF events reloadb and reloadc are not connected at device level Figure 1-5. Motor control module interfaces dc_bus_voltage async_event...
Page 47: Linphy Connectivity
Chapter 1 Device Overview MC9S12ZVMB-Family 1.8.7 LINPHY connectivity The VLINSUP supply is internally connected to the device VSUP pin. 1.8.8 FTMRZ connectivity The soc_erase_all_req input to the flash module is driven directly by a BDC erase flash request resulting from the BDC ERASE_FLASH command.
Page 48: Mc9S12Zvmb Family Reference Manual Rev. 1.3 Nxp Semiconductors
Writing to internal memory locations using the debugger, whilst code is running or at a breakpoint, can change the flow of application code. The MC9S12ZVMB-Family supports BDC communication throughout the device Stop mode. During Stop mode, writes to control registers can alter the operation and lead to unexpected results. It is thus recommended not to reconfigure the peripherals during STOP using the debugger.
Page 49: Security
Chapter 1 Device Overview MC9S12ZVMB-Family The key pad and SCI transceiver modules can be configured to wake the device, whereby current consumption is negligible. If the BDC is enabled, when the device enters Stop mode, the VREG remains in full performance mode.
Page 50: Operation Of The Secured Microcontroller
Chapter 1 Device Overview MC9S12ZVMB-Family Table 1-12. Security bits SEC[1:0] Security State 1 (secured) 1 (secured) 0 (unsecured) 1 (secured) NOTE Please refer to the flash block description for more security byte details. 1.10.3 Operation of the secured microcontroller By securing the device, unauthorized access to the EEPROM and Flash memory contents is prevented.
Page 51: Reprogramming The Security Bits
Chapter 1 Device Overview MC9S12ZVMB-Family • The application program programmed into the microcontroller has the capability to write to the back-door key locations The back-door key values themselves should not normally be stored within the application data, which means the application program would have to be designed to receive the back-door key values from an external source (e.g.
Page 52: Interrupt Vectors
Chapter 1 Device Overview MC9S12ZVMB-Family Table 1-13. Reset sources and vector locations Vector Address Reset Source Local Enable Mask 0xFFFFFC Power-On Reset (POR) None None Low Voltage Reset (LVR) None None External pin RESET None None Clock monitor reset None...
Page 53 Chapter 1 Device Overview MC9S12ZVMB-Family Table 1-14. Interrupt vector locations (Sheet 1 of 4) Wake up Wake up Vector Address Interrupt Source Local Enable Mask from STOP from WAIT Vector base + 0x1A4 Reserved Vector base + 0x1A0 SPI0 I bit...
Page 54 Chapter 1 Device Overview MC9S12ZVMB-Family Table 1-14. Interrupt vector locations (Sheet 1 of 4) Wake up Wake up Vector Address Interrupt Source Local Enable Mask from STOP from WAIT Vector base + 0x130 Reserved Vector base + 0x114 Vector base + 0x110...
Page 55: Effects Of Reset
Chapter 1 Device Overview MC9S12ZVMB-Family Table 1-14. Interrupt vector locations (Sheet 1 of 4) Wake up Wake up Vector Address Interrupt Source Local Enable Mask from STOP from WAIT Vector base + 0x08C TIM1 timer overflow I bit TIM1TSCR2(TOI) Vector base + 0x088...
Page 56: Flash Ifr Mapping
Chapter 1 Device Overview MC9S12ZVMB-Family GDUF register is also loaded from the Flash configuration field byte at global address 0xFF_FE0E during the reset sequence. See Table 1-15, Table 1-17 Table 1-17 for coding. Table 1-15. Initial COP rate configuration NV[2:0] in...
Page 57: Application Information
Chapter 1 Device Overview MC9S12ZVMB-Family 1.13 Application information 1.13.1 Temperature sensor The DVBE temperature sensor output is mapped to the ADC internal channel 7. It is tested in production at 26C, using conversions of ADC internal channel 7 and storing the result to the flash location 0x1F_C054, 0x1F_C055 as a 12-bit right aligned value.
Page 58 Chapter 1 Device Overview MC9S12ZVMB-Family 6.2 mV/C 6 mV/C Voltage (V) 5.8 mV/C 129.3 Temperature (C) Figure 1-6. DVBE effect of slope inaccuracy MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 59 Chapter 1 Device Overview MC9S12ZVMB-Family Furthermore the production test temperature control accuracy is limited to +/-3C. Figure 1-7 illustrates the effect of this limitation, whereby the value V actually corresponds to a test temperature of 29C. Thus, if configured to detect V + 600mV, the detection could be offset by 3C and in this case would...
Page 60: Sci Baud Rate Detection
Chapter 1 Device Overview MC9S12ZVMB-Family = (StoredReference/ConvertedReference) x 5V Eqn. 1-1 The absolute value of the DVBE conversion can be determined as follows: = ConvertedDVBE x (StoredReference/ConvertedReference) x 5V/2 Eqn. 1-2 DVBE ConvertedDVBE: Result of the analog to digital conversion of the DVBE...
Page 61 Chapter 1 Device Overview MC9S12ZVMB-Family Figure 1-8. DC brushed motor external configuration + 1/2 U - 1/2 U Usually the control consists of an outer, speed control loop with inner current (torque) control loop. The inner loop controls DC voltage applied onto the motor winding. The control loop is calculated regularly within a given period.
Page 62 Chapter 1 Device Overview MC9S12ZVMB-Family Assuming first quadrant operation, forward accelerating operation, the applied voltage at node A must exceed the applied voltage at node B (Figure 1-8). Thus the PWM0 duty cycle must exceed the PWM2 duty cycle. The PWM duty cycle of PWM0 defines the voltage at the first power stage branch.
Page 63: Power Domain Considerations
Chapter 1 Device Overview MC9S12ZVMB-Family 1.13.4 Power domain considerations The MC9S12ZVMB-Family power domains are illustrated in Figure 1-11. More detailed information is included in the individual module descriptions. Figure 1-11. Power domain overview VRBATP VSUPHS (12 V/18 V) VSUP (12 V/18 V)
Page 64 Chapter 1 Device Overview MC9S12ZVMB-Family connected directly internally. ESD protection diodes exist between VDDX and VDDA, therefore forcing a common operating range. The VDD domain supplies the internal device logic. The VDDF domain supplies sections of the internal Flash NVM circuitry.
Page 65 Chapter 1 Device Overview MC9S12ZVMB-Family PMFCINV = 0x0F; // Invert all channels to precharge bootstraps 1.13.4.4 High-side charge pump for 100% duty cycle A charge pump voltage is used to supply the High-side FET-predriver with enough current to maintain the gate source voltage.
Page 66 Chapter 1 Device Overview MC9S12ZVMB-Family Figure 1-12. High-side supply and charge pump concept VBAT VLS_OUT (11 V) 1 nF 10 nF 11 V GCPCD GCPE 1000 uF VBSx (Motor Dependent) GHGx High-side GHSx Low-side Diode voltage drop = Vdiode MC9S12ZVMB Family Reference Manual Rev. 1.3...
Page 67: Chapter 2
Chapter 2 Port Integration Module (S12ZVMBPIMV3) Table 2-1. Revision History Rev. No. Date (Submitted Sections Substantial Change(s) (Item No.) Affected V03.00 19 Jun 2015 • Initial release for S12ZVMB-family V03.01 7 Jul 2015 • Incorporated feedback from review V03.02 14 Jul 2015 2.3.2.6/2- •...
Page 68: Introduction
GPIO SCI1 Pins Oscillator DBGEE PTE1 TXD1 PWM1 XTAL PTE0 RXD1 PWM0 EXTAL • Port AD GPIO/KWU ADC0 SPI0 Pins PTADH0 AN0_8 PAD8 PTADL7 AN0_7 PAD7 PTADL6 AN0_6 PAD6 PTADL5 AN0_5 PAD5 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 69 PWM3 LP0RXD FAULT5 ECLK PTT1 IOC0_1 PWM2 MISO0 TXD0 TXD1 LP0DR1 PTT0 IOC0_0 MOSI0 RXD0 RXD1 XIRQ • Port P GPIO/KWU SPI0 LINPHY0 Pins PTP1 PWM5 SCK0 FAULT5 PTP0 PWM4 PTURE LP0TXD MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 70: Features
— Internal RXD0 and RXD1 link to TIM0 input capture channel (IC0_3) for baud rate detection — Internal ACLK link to TIM0 input capture channel (IC0_2) for calibration and clock monitoring purposes MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 71: External Signal Description
Table 2-2. BKGD Pin Functions and Priorities Func. Pin Function Routing Port Description after & Priority Register Bit Reset BKGD MODC MODC input during RESET — BKGD BKGD I/O S12ZBDC communication — 1. Function active when RESET asserted MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 72 I/O SCI1 transmit SCI1RR DBGEEV DBG external event — PTE[1] I/O GPIO — EXTAL — CPMU OSC signal — (PWM0) PWM channel 0 P0C0RR (RXD1) SCI1 receive SCI1RR PTE[0] I/O GPIO — MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 73 ADC0 analog input — PTADL[1]/ I/O GPIO with pin-interrupt and key-wakeup — KWADL[1] PAD0 AMPP0 GDU AMP0 non-inverting input (+) — ADC0 analog input — PTADL[0]/ I/O GPIO with pin-interrupt and key-wakeup — KWADL[0] MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 74 2. The interrupt is enabled by clearing the X mask bit in the CPU CCR. The pin is forced to input upon first clearing of the X bit and is held in this state until reset. A stop or wait recovery using XIRQ with the X bit set is not available. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 75 T1IC1RR AN10 ADC0 analog input AN10 PTIL[1]/ HVI with pin-interrupt and key-wakeup — KWL[1] IOC1_0 TIM1 input capture channel 0 T1IC0RR ADC0 analog input PTIL[0]/ HVI with pin-interrupt and key-wakeup — KWL[0] MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 76: Internal Routing Options
This section provides a detailed description of all port integration module registers. Subsection 2.3.1 shows all registers and bits at their related addresses within the global SOC register map. A detailed description of every register bit is given in subsections 2.3.2 to 2.3.4. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 77: Register Map
Reserved 0x020C 0x020D Reserved Reserved Reserved 0x020E Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x020F Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x0210– Reserved 0x025F 0x0260 PTE1 PTE0 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 78 PTADL1 PTADL0 PTIADH0 0x0282 PTIADH R PTIADL7 PTIADL6 PTIADL5 PTIADL4 PTIADL3 PTIADL2 PTIADL1 PTIADL0 0x0283 PTIADL 0x0284 DDRADH DDRADH0 0x0285 DDRADL DDRADL7 DDRADL6 DDRADL5 DDRADL4 DDRADL3 DDRADL2 DDRADL1 DDRADL0 0x0286 PERADH PERADH0 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 79 PTT1 PTT0 PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 0x02C1 PTIT 0x02C2 DDRT DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 0x02C3 PERT PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 80 RDRT2 0x02CE– Reserved 0x02CF 0x02D0– Reserved 0x02EF 0x02F0 PTP1 PTP0 PTIP1 PTIP0 0x02F1 PTIP 0x02F2 DDRP DDRP1 DDRP0 0x02F3 PERP PERP1 PERP0 0x02F4 PPSP PPSP1 PPSP0 0x02F5 Reserved 0x02F6 PIEP PIEP1 PIEP0 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 81 0x02FE– Reserved 0x02FF 0x0300– Reserved 0x032F 0x0330 Reserved PTIL2 PTIL1 PTIL0 0x0331 PTIL 0x0332 Reserved 0x0333 PTPSL PTPSL2 PTPSL1 PTPSL0 0x0334 PPSL PPSL2 PPSL1 PPSL0 0x0335 Reserved 0x0336 PIEL PIEL2 PIEL1 PIEL0 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 82: Pim Registers 0X0200-0X020F
If not stated differently, writing to reserved bits has no effect and read returns zero. • All register read accesses are synchronous to internal clocks. • Register bits can be written at any time if not stated differently. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 83 Table 2-11 for preferred settings. Note: SCI0 must be enabled for TXD0 routing to take effect on pin. LINPHY0 must be enabled for LPRXD0 and LPDR[LPDR1] routings to take effect on pins. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 84 Interface opened and all 4 signals routed externally NOTE For standalone usage of SCI0 on external pins set S0L0RR[2:0]=0b110 and disable LINPHY0 (LPCR[LPE]=0). This releases the LINPHY0 associated pins to other shared functions. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 85 2.3.2.3 Module Routing Register 2 (MODRR2) Address 0x0202 Access: User read/write — — — — — — — — Reset Figure 2-4. Module Routing Register 2 (MODRR2) 1. Read: Anytime Write: Never MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 86 P0C2RR P0C1RR P0C0RR Routing FAULT5 — PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 Option Reset Figure 2-6. Module Routing Register 4 (MODRR4) 1. Read: Anytime Write: Once in normal, anytime in special mode MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 87 T1IC2RR T1IC1RR T1IC0RR T1OC2RR T1OC1RR IC1_3 IC1_2 IC1_1 IC1_0 — OC1_2 OC1_1 — Reset Figure 2-7. Module Routing Register 1 (MODRR5) 1. Read: Anytime Write: Once in normal, anytime in special mode MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 88 0 TIM1 output compare channel 2 connected to PT6 Module Routing Register — OC1_1 routing T1OC1RR 1 TIM1 output compare channel 1 connected to HS0 0 TIM1 output compare channel 1 connected to PT5 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 89 IRQE=1 and will be cleared only upon a reset or the servicing of the IRQ interrupt. 0 IRQ configured for low level recognition IRQ enable — IRQEN 1 IRQ pin is connected to interrupt logic 0 IRQ pin is disconnected from interrupt logic MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 90 Write: Only in special mode This reserved register is designed for factory test purposes only and is not intended for general user access. Writing to this register when in special modes can alter the modules functionality. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 91: Pim Generic Registers
For availability of individual bits refer to Section 2.3.1, “Register Map” and Table 2-44. NOTE This is a generic description of the standard PIM registers. Refer to Table 2- to determine the implemented bits in the respective register. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 92 Port Input — Data input PTIx7-0 A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit conditions on output pins. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 93 Access: User read/write 0x0286 PERADH 0x0287 PERADL 0x02C3 PERT 0x02F3 PERP PERx7 PERx6 PERx5 PERx4 PERx3 PERx2 PERx1 PERx0 Reset Ports E: Others: Figure 2-16. Pull Device Enable Register 1. Read: Anytime Write: Anytime MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 94 2.3.3.6 Port Interrupt Enable Register Address 0x028C PIEADH Access: User read/write 0x028D PIEADL 0x02F6 PIEP 0x0336 PIEL PIEx7 PIEx6 PIEx5 PIEx4 PIEx3 PIEx2 PIEx1 PIEx0 Reset Figure 2-18. Port Interrupt Enable Register MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 95 Writing a logic “1” to the corresponding bit field clears the flag. 1 Active edge on the associated bit has occurred 0 No active edge occurred MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 96 The reduced drive function is independent of which function is being used on a particular pin. 1 Reduced drive selected (approx. 1/10 of the full drive strength) 0 Full drive strength enabled MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 97: Pim Generic Register Exceptions
1 Pulldown device selected; rising edge selected; active-high level selected on FAULT5 input 0 Pullup device selected; falling edge selected; active-low level selected on FAULT5 input Section 2.3.3.5, “Polarity Select Register”. PPST1-0 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 98 Table 2-29. OCIET Register Field Descriptions Field Description Over-Current Interrupt Enable — OCIET2 This bit enables or disables the over-current interrupt on PT2. 1 PT2 over-current interrupt enabled 0 PT2 over-current interrupt disabled (interrupt flag masked) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 99 1 Pulldown device selected; rising edge selected; active-high level selected on FAULT5 input 0 Pullup device selected; falling edge selected; active-low level selected on FAULT5 input Section 2.3.3.5, “Polarity Select Register”. PPSP0 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 100 Table 2-33. OCIEP Register Field Descriptions Field Description Over-Current Interrupt Enable — OCIEP0 This bit enables or disables the over-current interrupt on PP0. 1 PP0 over-current interrupt enabled 0 PP0 over-current interrupt disabled (interrupt flag masked) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 101 This flag asserts if an over-current condition is detected on PP0 (Section 2.4.5.3, “Over-Current Interrupt and Protection”). Writing a logic “1” to the corresponding bit field clears the flag. 1 PP0 over-current event occurred 0 No PP0 over-current event occurred MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 102 If this bit set to 1 and PTTEL=1 and not in stop mode a pullup to a level close to V takes effect and overrides the weak pulldown device. Refer to Section 2.5.5, “Open Input Detection on PL[2:0] (HVI)”). 1 Pullup enabled 0 Pulldown enabled MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 103 This bit bypasses and powers down the impedance converter stage in the signal path from the analog input pin to the ADC channel input. This bit takes effect only if using direct input connection to the ADC channel (PTADIRL=1). 1 Impedance converter bypassed 0 Impedance converter used MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 104 0 Associated pin digital input is disabled 1. Refer to PTTEL bit description in Section 2.3.4.15, “Port L ADC Connection Enable Register (PTAENL) for an override condition. 2. “Stop mode” is limited to RPM; refer to Table 2-47. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 105 Port L Input Divider Ratio Select — PIRL2-0 This bit selects one of two voltage divider ratios for the associated HVI pin in analog mode. 1 Ratio selected L_HVI 0 Ratio selected H_HVI MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 106: Functional Description
For example a pullup device does not become active while the port is used as a push-pull output. Unimplemented bits read zero. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 107: Pin I/O Control
The general-purpose data direction configuration can be overruled by an enabled peripheral function shared on the same pin (Table 2-45). If more than one peripheral function is available and enabled at the MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 108: Pull Devices
If a pin is used as open-drain output (WOMx=1) then the pulldown device is disabled. 2.4.5 Interrupts This section describes the interrupts generated by the PIM and their individual sources. Vector addresses and interrupt priorities are defined at MCU level. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 109 > t guarantee a wakeup event. PULSE P_PASS Please refer to the appendix table “Pin Timing Characteristics” for pulse length limits. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 110: High-Voltage Input
HVI. NOTE The term stop mode (STOP) is limited to voltage regulator operating in reduced performance mode (RPM). Refer to “Low Power Modes” section in device overview. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 111 PTTEL=1 & PTADIRL=0) and the voltage applied to a selectable HVI pin can be measured on its related ADC channel (refer to device overview section for channel assignment). One of two input divider MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 112: Initialization And Application Information
SCI Baud Rate Detection The baud rate for SCI0 and SCI1 can be determined by using a timer channel to measure the data rate on the related RXD signal. 1. Establish the link: MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 113: Over-Current Protection On Pp0 (Evdd)
HVI in analog mode. Make sure to switch off the override function when using the HVI in analog mode after the check has been completed. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 114 2. Select internal pulldown device on HVI (PTPSL=0) 3. Enable function to force input buffer active on HVI in analog mode (PTTEL=1) 4. Verify PTIL=1 for a connected external pullup device; read PTIL=0 for an open input MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 115 Chapter 2 Port Integration Module (S12ZVMBPIMV3) HV Supply max. 10/11 * V (PIRL=0) max. 21/22 * V (PIRL=1) Digital in 610K / 1050K PIRL=0 / PIRL=1 Figure 2-44. Digital Input Read with Pulldown Enabled MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 116 Chapter 2 Port Integration Module (S12ZVMBPIMV3) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 117: Introduction
Chapter 3 Memory Mapping Control (S12ZMMCV1) Table 3-1. Revision History Revision Sections Revision Date Description of Changes Number Affected V01.05 6 Aug 2012 Fixed wording Figure 3-8 • Changed “KByte:to “KB” V01.06 12 Feb 2013 3.3.2.2/3-122 • Corrected the description of the MMCECH/L register •...
Page 118: Glossary
The S12ZMMC determines the chip configuration mode of the device. It captures the state of the MODC pin at reset and provides the ability to switch from special-single chip mode to normal single chip-mode. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 119: Block Diagram
3.3.1 Memory Map A summary of the registers associated with the MMC block is shown in Figure 3-2. Detailed descriptions of the registers and bits are given in the subsections that follow. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 120: Register Descriptions
0x0087 MMCPCL CPUPC[7:0] 0x0088- Reserved 0x00FF = Unimplemented or Reserved Figure 3-2. S12ZMMC Register Summary 3.3.2 Register Descriptions This section consists of the S12ZMMC control and status register descriptions in address order. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 121 Reset with Reset with MODC pin = 1 MODC pin = 0 Normal Special Single-Chip Single-Chip Mode (NS) write access to Mode (SS) MODE: 1  MODC bit Figure 3-4. Mode Transition Diagram MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 122 Target Field — The TGT[3:0] bits capture the target of the faulty access. The target is captured in form of a (MMCECH) TGT[3:0] 4 bit value which is assigned as follows: 0: none 1: register space 2: RAM 3: EEPROM 4: program flash 5: IFR 6-15: reserved MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 123 3.3.2.3 Captured S12ZCPU Condition Code Register (MMCCCRH, MMCCCRL) Address: 0x0082 (MMCCCRH) CPUU Reset Address: 0x0083 (MMCCCRL) CPUX CPUI Reset Figure 3-6. Captured S12ZCPU Condition Code Register (MMCCCRH, MMCCCRL) Read: Anytime Write: Never MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 124 Captured S12ZCPU Program Counter (MMCPCH, MMCPCM, MMCPCL) Address: 0x0085 (MMCPCH) CPUPC[23:16] Reset Address: 0x0086 (MMCPCM) CPUPC[15:8] Reset Address: 0x0087 (MMCPCL) CPUPC[7:0] Reset Figure 3-7. Captured S12ZCPU Program Counter (MMCPCH, MMCPCM, MMCPCL) Read: Anytime Write: Never MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 125: Functional Description
The S12ZMMC maps all on-chip resources into an 16MB address space, the global memory map. The exact resource mapping is shown in Figure 3-8. The global address space is used by the S12ZCPU, ADC, and the S12ZBDC module. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 126 6 KBKB 0x1F_C000 NVM IFR 256 Byte 0x20_0000 Unmapped 6 MByte 0x80_0000 Program NVM max. 8 MByte Unmapped address range Low address aligned High address aligned 0xFF_FFFF Figure 3-8. Global Memory Map MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 127: Illegal Accesses
Illegal accesses are reported in several ways: • All illegal accesses performed by the S12ZCPU trigger machine exceptions. • All illegal accesses performed through the S12ZBDC interface, are captured in the ILLACC bit of the BDCCSRL register. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 128: Uncorrectable Ecc Faults
S12ZCPU or ADC access triggers a machine exception. Uncorrectable memory corruptions which are detected during a S12ZBDC access, are captured in the RAMWF or the RDINV bit of the BDCCSRL register. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 129: Introduction
Chapter 4 Interrupt (S12ZINTV0) Table 4-1. Revision History Version Revision Effective Description of Changes Number Date Date V00.01 17 Apr 2009 Initial version based on S12XINT V2.06 V00.02 14 Jul 2009 Reduce RESET vectors from three to one. V00.03 05 Oct 2009 Removed dedicated ECC machine exception vector and marked vector-table entry “reserved for future use”.
Page 130: Glossary
1. The vector base is a 24-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used as the upper 15 bits of the address) and 0x000 (used as the lower 9 bits of the address). MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 131: Modes Of Operation
In stop mode, the INT module is capable of waking up the CPU if an eligible CPU exception occurs. Please refer to Section 4.5.3, “Wake Up from Stop or Wait Mode” for details. 4.1.4 Block Diagram Figure 4-1 shows a block diagram of the INT module. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 132: External Signal Description
INT module registers. Table 4-3. INT Memory Map Address Access 0x000010–0x000011 Interrupt Vector Base Register (IVBR) 0x000012–0x000016 RESERVED — 0x000017 Interrupt Request Configuration Address Register (INT_CFADDR) 0x000018 Interrupt Request Configuration Data Register 0 (INT_CFDATA0) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 133: Register Descriptions
0x000017 INT_CFADDR R INT_CFADDR[6:3] 0x000018 INT_CFDATA0 R PRIOLVL[2:0] 0x000019 INT_CFDATA1 R PRIOLVL[2:0] 0x00001A INT_CFDATA2 R PRIOLVL[2:0] 0x00001B INT_CFDATA3 R PRIOLVL[2:0] 0x00001C INT_CFDATA4 R PRIOLVL[2:0] = Unimplemented or Reserved Figure 4-2. INT Register Summary MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 134 Therefore, changing the IVBR has no effect on the location of the reset vector (0xFFFFFC–0xFFFFFF). 4.3.2.2 Interrupt Request Configuration Address Register (INT_CFADDR) Address: 0x000017 INT_CFADDR[6:3] Reset = Unimplemented or Reserved Figure 4-4. Interrupt Configuration Address Register (INT_CFADDR) Read: Anytime MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 135 Figure 4-6. Interrupt Request Configuration Data Register 1 (INT_CFDATA1) 1. Please refer to the notes following the PRIOLVL[2:0] description below. Address: 0x00001A PRIOLVL[2:0] Reset = Unimplemented or Reserved Figure 4-7. Interrupt Request Configuration Data Register 2 (INT_CFDATA2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 136 1. Please refer to the notes following the PRIOLVL[2:0] description below. Address: 0x00001E PRIOLVL[2:0] Reset = Unimplemented or Reserved Figure 4-11. Interrupt Request Configuration Data Register 6 (INT_CFDATA6) 1. Please refer to the notes following the PRIOLVL[2:0] description below. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 137: Functional Description
The INT module processes all exception requests to be serviced by the CPU module. These exceptions include interrupt vector requests and reset vector requests. Each of these exception types and their overall priority level is discussed in the subsections below. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 138: S12Z Exception Requests
CPU. The copying takes place when the interrupt vector is fetched. The previous IPL is automatically restored from the stack by executing the RTI instruction. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 139: Priority Decoder
(Vector base + 0x0001F4) Unimplemented page2 op-code trap (TRAP) vector request (Vector base + 0x0001F0) Software interrupt instruction (SWI) vector request (Vector base + 0x0001EC) System call interrupt instruction (SYS) vector request MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 140: Interrupt Vector Table Layout
I-bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority, so that there can be up to seven nested I-bit maskable interrupt requests at a time (refer to Figure 4- for an example using up to three nested interrupt requests). MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 141: Wake Up From Stop Or Wait Mode
The X-bit maskable interrupt request can wake up the MCU from stop or wait mode at anytime, even if the X-bit in CCW is set . If the X-bit maskable interrupt request is used to wake-up the MCU with the X- MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 142 1. The capability of the XIRQ pin to wake-up the MCU with the X bit set may not be available if, for example, the XIRQ pin is shared with other peripheral modules on the device. Please refer to the Port Integration Module (PIM) section of the MCU reference manual for details. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 143: Introduction
Chapter 5 Background Debug Controller (S12ZBDCV2) Table 5-1. Revision History Revision Revision Sections Description of Changes Number Date Affected V2.04 03.Dec.2012 Section 5.1.3.3, Included BACKGROUND/ Stop mode dependency “Low-Power Modes V2.05 22.Jan.2013 Section 5.3.2.2, Improved NORESP description and added STEP1/ Wait mode dependency “BDC Control Status Register Low (BDCCSRL)
Page 144: Glossary
5.1.3.2 Security and Operating mode Dependency In device run mode the BDC dependency is as follows • Normal modes, unsecure device General BDC operation available. The BDC is disabled out of reset. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 145 Furthermore if a BDC internal access is being executed when the device is entering stop mode, then the stop mode entry is delayed until the internal access is complete (typically for 1 bus clock cycle). MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 146 Active-Background commands set NORESP and ILLCMD because the BDC is not in active BDM state. With ACK enabled, if the host attempts further communication before the ACK pulse generation then the OVRUN bit is set. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 147: Block Diagram
Refer to Section 5.4.6, “BDC Serial Interface” for more details. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 148: Memory Map And Register Definition
ENBDC BDCCIS STEAL CLKSW Reset Secure AND SSC-Mode Unsecure AND SSC-Mode Secure AND NSC-Mode Unsecure AND NSC-Mode = Unimplemented, Reserved = Always read zero Figure 5-3. BDC Control Status Register High (BDCCSRH) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 149 Reading this bit indicates the status of the requested mass erase sequence. 0 No flash mass erase sequence pending completion 1 Flash mass erase sequence pending completion. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 150 RAM Write Fault — Indicates an ECC double fault during a BDC write access to RAM. RAMWF Writing a “1” to this bit, clears the bit. 0 No RAM write double fault detected. 1 RAM write double fault detected. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 151 (Section 5.4.5.1, “BDC Access Of CPU Registers). Illegal accesses return a value of 0xEE for each data byte Writing a “1” to this bit, clears the bit. 0 No illegal access detected. 1 Illegal BDC access detected. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 152: Functional Description
After resetting into SSC mode, the initial PC address must be supplied by the host using the WRITE_Rn command before issuing the GO command. 1. BDM active immediately out of special single-chip reset. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 153: Clock Source
BDCSI Clock and FSM BDCFCLK CLKSW BDC device resource interface Core clock Figure 5-5. Clock Switch 5.4.4 BDC Commands BDC commands can be classified into three types as shown in Table 5-7. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 154 BDC shift register before the write has been completed. The external host must wait at least for 16 bdcsi cycles after a control command before starting any new serial command. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 155 ACK_ENABLE Always 0x02/dack Enable the communication handshake. Available Issues an ACK pulse after the command is executed. BACKGROUND Non-Intrusive 0x04/dack Halt the CPU if ENBDC is set. Otherwise, ignore as illegal command. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 156 READ_MEM.sz_WS Non-Intrusive (0x31+4 x sz)/ad24/d/ss/rd.sz Read the appropriately-sized (sz) memory value from the location specified by the 24- bit address and report status READ_DBGTB Non-Intrusive (0x07)/dack/rd32/dack/rd32 Read 64-bits of DBG trace buffer MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 157 BDCSI clock). 4. Removes all drive to the BKGD pin so it reverts to high impedance. 5. Listens to the BKGD pin for the sync response pulse. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 158 Disables the serial communication handshake protocol. The subsequent commands, issued after the ACK_DISABLE command, do not execute the hardware handshake protocol. This command is not followed by an ACK pulse. 5.4.4.3 ACK_ENABLE Enable host/target handshake protocol Always Available 0x02 host  target MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 159 The host can recognize this pending BDM request condition because both NORESP and WAIT are set, but BDMACT is clear. Whilst in wait mode, with the pending BDM request, non-intrusive BDC commands are allowed. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 160 (1, 2, or 4) and saved in a temporary register. Subsequent DUMP_MEM{_WS} commands use this address, perform the memory read, increment it by the current operand size, and store the updated address in the temporary register. If the with-status option is specified, MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 161  target target target target target FILL_MEM.sz_WS Write memory specified by debug address register with Non-intrusive status, then increment address 0x13 Data[7-0] BDCCSRL host  host  target  target target host MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 162 This command is used to exit active BDM and begin (or resume) execution of CPU application code. The CPU pipeline is flushed and refilled before normal instruction execution resumes. Prefetching begins at MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 163 If ACK handshaking is disabled, the GO_UNTIL command is identical to the GO command. 5.4.4.9 No operation Active Background 0x00 host  target NOP performs no operation and may be used as a null command where required. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 164  target  target target host host 0x38 Address[23-0] Data[31-24] Data[23-16] Data[15-8] Data[7-0] host  host  target  target  target  target  target target host host host host MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 165 After issuing the first ACK a timeout is still possible whilst accessing the second 32-bit longword, since this requires separate internal accesses. The first 32-bit longword corresponds to trace buffer line MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 166 NOP can be used for inter-command padding without corrupting the address pointer. 5.4.4.14 READ_BDCCSR Read BDCCSR Status Register Always Available BDCCSR BDCCSR 0x2D [15:8] [7-0] host  target target  host  host target MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 167 PC address of the instruction currently being executed by the CPU. In active BDM, SYNC_PC returns the address of the next instruction to be executed on returning from active BDM. Thus following a write to the PC in active BDM, a SYNC_PC returns that written value. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 168 This status byte reflects the state after the memory write was performed. The examples show the WRITE_MEM.B{_WS}, WRITE_MEM.W{_WS}, and WRITE_MEM.L{_WS} commands. If enabled an ACK pulse is generated after the internal write access has been completed or aborted. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 169 Mass erase the internal flash. This command can always be issued. On receiving this command twice in succession, the BDC sets the ERASE bit in BDCCSR and requests a flash mass erase. Any other BDC command following a single ERASE_FLASH initializes the sequence, such that thereafter the MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 170: Bdc Access Of Internal Resources
Illegal address access, whereby ILLACC is set • Invalid READ_SAME or DUMP_MEM sequence • Invalid READ_Rn command (BDM inactive or CRN incorrect) • Internal resource read with timeout, whereby NORESP is set MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 171 5-10. Thus if address bits [1:0] are both logic “1” the access is realigned so that it does not straddle the 4-byte boundary but accesses data from within the addressed 4-byte field. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 172 Accessed Accessed Accessed DUMP_MEM.32 0x004004 Accessed Accessed Accessed Accessed DUMP_MEM.16 0x004008 Accessed Accessed DUMP_MEM.16 0x00400A Accessed Accessed DUMP_MEM.08 0x00400C Accessed DUMP_MEM.16 0x00400D Accessed Accessed DUMP_MEM.16 0x00400E Accessed Accessed DUMP_MEM.16 0x004010 Accessed Accessed MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 173: Bdc Serial Interface
BDC. The BDC serial interface uses an internal clock source, selected by the CLKSW bit in the BDCCSR register. This clock is referred to as the target clock in the following explanation. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 174 1 from the target system. The host holds the BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must release the low MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 175 Since the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 target clock cycles after starting the bit time. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 176: Serial Interface Hardware Handshake (Ack Pulse) Protocol
ACK PULSE 32 CYCLES SPEED UP PULSE MINIMUM DELAY FROM THE BDC COMMAND BKGD PIN EARLIEST 16th CYCLE OF THE START OF LAST COMMAND BIT NEXT BIT Figure 5-9. Target Acknowledge Pulse (ACK) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 177 BDC DECODES COMMAND THE COMMAND Figure 5-10. Handshake Protocol at Command Level Alternatively, setting the STEAL bit configures the handshake protocol to make an immediate internal access, independent of free bus cycles. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 178: Hardware Handshake Abort Procedure
“SYNC”. Figure 5-11 shows a SYNC command being issued after a READ_MEM, which aborts the READ_MEM command. Note that, after the command is aborted a new command is issued by the host. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 179: Hardware Handshake Disabled (Ack Pulse Disabled)
If the ACK pulse protocol is disabled, the host needs to use the worst case delay time at the appropriate places in the protocol. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 180: Single Stepping
STEP1 has actually not finished. When an interrupt occurs the device leaves wait mode, enters active BDM and the PC points to the start of the corresponding interrupt service routine. A further ACK related to stepping over the WAI is not generated. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 181: Serial Communication Timeout
BDCSI clock frequency is expressed by Minimum f = (3/(#DLY cycles -4))f (core clock) (BDCSI clock) For the standard 16 period DLY this yields f >= (1/4)f (core clock) (BDCSI clock) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 182 Chapter 5 Background Debug Controller (S12ZBDCV2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 183: Introduction
Chapter 6 S12Z DebugLite (S12ZDBGV3) Module Table 6-1. Revision History Table Revision Revision Sections Description Of Changes Number Date Affected 3.00 23.MAY.2012 General Updated for DBGV3 using conditional text 3.01 27.JUN.2012 General Added Lite to module name. Corrected DBGEFR register format issue 3.02 05.JUL.2012 Section 6.3.2.6,...
Page 184: Glossary
— State transitions forced by software write to TRIG — State transitions forced by an external event • The following types of breakpoints — CPU breakpoint entering active BDM on breakpoint (BDM) — CPU breakpoint executing SWI on breakpoint (SWI) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 185: Modes Of Operation
2 bus cycles after they occur at the pin. Thus an external event occurring less than 2 bus cycles before arming the DBG module is perceived to occur whilst the DBG is armed. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 186: Memory Map And Registers
0x0109 DBGSCR3 C3SC1 C3SC0 C1SC1 C1SC0 C0SC1 C0SC0 TRIGF EEVF 0x010A DBGEFR SSF2 SSF1 SSF0 0x010B DBGSR 0x010C- Reserved 0x010F 0x0110 DBGACTL INST reserved COMPE Figure 6-2. Quick Reference to DBG Registers MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 187 Bit 0 0x0120 DBGBCTL INST reserved COMPE 0x0121- Reserved 0x0124 0x0125 DBGBAH DBGBA[23:16] 0x0126 DBGBAM DBGBA[15:8] 0x0127 DBGBAL DBGBA[7:0] 0x0128- Reserved 0x012F 0x0130- Reserved 0x013F Figure 6-2. Quick Reference to DBG Registers MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 188: Register Descriptions
Bits 5:0 anytime DBG is not armed. NOTE On a write access to DBGC1 and simultaneous hardware disarm from an internal event, the hardware disarm has highest priority, clearing the ARM bit and generating a breakpoint, if enabled. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 189 Debug Control Register2 (DBGC2) Address: 0x0101 ABCM Reset = Unimplemented or Reserved Figure 6-4. Debug Control Register2 (DBGC2) Read: Anytime. Write: Anytime the module is disarmed. This register configures the comparators for range matching. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 190 If EEVE !=10, these bits select the targeted next state whilst in State1 following a match3. If EEVE = 10, these bits select the targeted next state whilst in State1 following an external event. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 191 Match forces sequencer to State1 Match forces sequencer to State3 Match forces sequencer to Final State In the case of simultaneous matches, the match on the higher channel number (3...0) has priority. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 192 In the case of simultaneous matches, the match on the higher channel number (3..0) has priority. 6.3.2.6 Debug Event Flag Register (DBGEFR) Address: 0x010A TRIGF EEVF Reset = Unimplemented or Reserved Figure 6-9. Debug Event Flag Register (DBGEFR) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 193 State0 and these bits are cleared to indicate that State0 was entered during the session. On arming the module the state sequencer enters State1 and these bits are forced to SSF[2:0] = 001. See Table 6-15 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 194 0 Read/Write is not used in comparison 1 Read/Write is used in comparison Enable Bit — Determines if comparator is enabled COMPE 0 The comparator is not enabled 1 The comparator is enabled MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 195 DBGAA the address bus bits [15:0] to a logic one or logic zero. [15:0] 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 196 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Figure 6-14. Debug Comparator A Data Mask Register (DBGADM) Read: Anytime. Write: If DBG not armed. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 197 Enable Bit — Determines if comparator is enabled COMPE 0 The comparator is not enabled 1 The comparator is enabled 1. If the ABCM field selects range mode comparisons, then DBGACTL bits configure the comparison, DBGBCTL is ignored. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 198 DBGBA the address bus bits [15:0] to a logic one or logic zero. [15:0] 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 199 Table 6-25. Read or Write Comparison Logic Table RWE Bit RW Bit RW Signal Comment RW not used in comparison RW not used in comparison Write match No match No match Read match MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 200: Functional Description
Figure 6-1. The comparators monitor the bus activity of the CPU. Comparators can be configured to monitor opcode addresses (effectively the PC address) or data accesses. Comparators can be configured during data MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 201: Comparator Modes
Match[0, 1, 3] map directly to Comparators [A, B, D] respectively, except in range modes (see Section 6.3.2.2, “Debug Control Register2 (DBGC2)”). Comparator priority rules are described in the event priority section (Section 6.4.3.4, “Event Priorities”). MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 202 32-bits and can only generate a match on a 32-bit access with correct 32- bit data value. In this case, 8-bit or 16-bit accesses within the 32-bit field cannot generate a match even if MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 203 Bytes that are not accessed are ignored. Thus when monitoring a multi byte field for a difference, partial accesses of the field only return a match if a difference is detected in the accessed bytes. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 204: Events
Events are used as qualifiers for a state sequencer change of state. The state control register for the current state determines the next state for each event. An event can immediately initiate a transition to the next state sequencer state whereby the corresponding flag in DBGSR is set. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 205 If a write access to DBGC1 with the ARM bit position set occurs simultaneously to a hardware disarm from an internal event, then the ARM bit is cleared due to the hardware disarm. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 206: State Sequence Control
State0. 6.4.5 Breakpoints Breakpoints can be generated by state sequencer transitions to State0. Transitions to State0 are forced by the following events • Through comparator matches via Final State. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 207: Application Information
Avoiding Unintended Breakpoint Re-triggering Returning from an instruction address breakpoint using an RTI or BDC GO command without PC modification, returns to the instruction that generated the breakpoint. If an active breakpoint or trigger still MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 208: Breakpoints From Other S12Z Sources
In this case the SWI routine is executed twice before returning. 6.5.2 Breakpoints from other S12Z sources The DBG is neither affected by CPU BGND instructions, nor by BDC BACKGROUND commands. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 209: Introduction
Chapter 7 ECC Generation Module (SRAM_ECCV3) Table 7-1. Revision History Table Rev. No. Sections Date Substantial Change(s) (Item No.) Affected V01.00 26-Jul.-11 Initial version V1 V02.00 10-May-12 Initial version V2, added support for max access width of 2 byte V03.00 31-Mar-15 describe the new behavior in case of non-aligned write to Double Bit ECC error memory location...
Page 210: Memory Map And Register Definition
Memory Map and Register Definition This section provides a detailed description of all memory and registers for the SRAM_ECC module. 7.2.1 Register Summary Figure 7-1 shows the summary of all implemented registers inside the SRAM_ECC module. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 211 0x0009 DPTR[7:1] ECCDPTRL 0x000A - 0x000B Reserved 0x000C DDATA[15:8] ECCDDH 0x000D DDATA[7:0] ECCDDL 0x000E DECC[5:0] ECCDE 0x000F ECCDRR ECCDW ECCDR ECCDCMD = Unimplemented, Reserved, Read as zero Figure 7-1. SRAM_ECC Register Summary MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 212: Register Descriptions
Table 7-3. ECCIE Field Description Field Description Single bit ECC Error Interrupt Enable — Enables Single ECC Error interrupt. SBEEIE 0 Interrupt request is disabled 1 Interrupt will be requested whenever SBEEIF is set MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 213 Single bit ECC Error Interrupt Flag — The flag is set to 1 when a single bit ECC error occurs. SBEEIF 0 No occurrences of single bit ECC error since the last clearing of the flag 1 Single bit ECC error has occurred since the last clearing of the flag MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 214 There is no additional monitoring of the register content; therefore, the software must make sure that the address value points to the system memory space. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 215 ECC Debug ECC — This register contains the raw ECC value which will be written into the system memory DECC[5:0] during a debug write command or the ECC read value from the debug read command. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 216: Functional Description
Table 7-9. Memory access cycles access Memory Access type Internal operation Error indication error cycle content Aligned write — write to memory new data — MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 217: Aligned Memory Write Access
A new ECC value will be calculated based on the undefined write data word. ECC value and the new write data word will be written into the memory. Therefore the data written to the memory are ECC clean. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 218: Memory Read Access
RDY status bit is set. 7.3.5 Interrupt Handling This section describes the interrupts generated by the SRAM_ECC module and their individual sources. Vector addresses and interrupt priority are defined at the MCU level. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 219: Ecc Algorithm
If the debug write access is done, the ECCDW register bit is cleared. The debug write access is always a 2 byte aligned memory access, so that no ECC check is performed and no single or double bit ECC error indication is activated. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 220 32-bit misaligned read. Thus a subsequent debug access of the lower 16-bit field returns uncorrected data. If the ECCDW and the ECCDR bits are set at the same time, then only the debug write access is performed. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 221: Introduction
Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V11) Revision History Table 8-1. Rev. No. Date Sections Affected Substantial Change(s) (Item No) (Submitted By) • initial version for VMB64, copied from ZVL128 • removed VREG5VEN Bit 18 May 2015 •...
Page 222: Features
PLL clock monitor reset • Reference clock either external (crystal) or internal square wave (1MHz IRC1M) based. • PLL stability is sufficient for LIN communication in slave mode, even if using IRC1M as reference clock MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 223 — Low-voltage reset (LVR) — COP system watchdog, COP reset on time-out, windowed COP — Loss of oscillation (Oscillator clock monitor fail) — Loss of PLL clock (PLL clock monitor fail) — External pin RESET MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 224: Modes Of Operation
— This mode can be entered from default mode PEI by performing the following steps: – Make sure the PLL configuration is valid for the selected oscillator frequency. – Enable the external oscillator (OSCE bit). MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 225 COP is stopped during Full Stop Mode and COP continues to operate after exit from Full Stop Mode. For this COP configuration (ACLK clock source, CSAD set) a latency time (please refer MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 226 Additionally the COP can be forced to the maximum time-out period in Active BDM Mode. For details please see also the RSBCK and CR[2:0] bit description field of Table 8-14 Section 8.3.2.12, “S12CPMU_UHV_V11 COP Control Register (CPMUCOP) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 227: S12Cpmu_Uhv_V11 Block Diagram
Osc. RTI Interrupt RTIE COP time-out COPCLK IRCCLK to Reset Watchdog Generator IRCCLK Real Time OSCCLK RTICLK Interrupt (RTI) OSCCLK CPMUCOP COPOSCSEL0 RTIOSCSEL CPMURTI UPOSC=0 clears Figure 8-1. Block diagram of S12CPMU_UHV_V11 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 228 Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V11) Figure 8-2 shows a block diagram of the XOSCLCP. OSCMOD monitor fail Clock Monitor OSCCLK Peak Gain Control Detector VDD=1.8V Quartz Crystals XTAL EXTAL Ceramic Resonators Figure 8-2. XOSCLCP Block Diagram MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 229: Signal Description
VDDA has to be connected externally to VDDX. 8.2.5 VDDX, VSSX — Pad Supply Pins VDDX is the supply domain for the digital Pads. An off-chip decoupling capacitor (10F plus 220 nF(X7R ceramic)) between VDDX and VSSX is required. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 230: Bctl — Base Control Pin For External Pnp
DVBE TEMPSENSE — DVBE Internal Temperature Sensor Output Voltage The voltage level generated by the DVBE temperature sensor is driven to a channel input of the ADC. See device level specification for connectivity of ADC channels. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 231: Memory Map And Registers
OSCSEL1 OSCSEL OSCSEL0 0x000A CPMUPLL 0x000B CPMURTI RTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0 0x000C CPMUCOP WCOP RSBCK WRTMASK RESERVED 0x000D CPMUTEST0 = Unimplemented or Reserved Figure 8-3. CPMU Register Summary MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 232 IRCTRIM[7:0] IRCTRIML 0x001A CPMUOSC OSCE Reserved 0x001B CPMUPROT PROT RESERVED 0x001C CPMUTEST2 CPMU 0x001D EXTXON INTXON VREGCTL 0x001E CPMUOSC2 OMRE OSCMOD 0x001F RESERVED = Unimplemented or Reserved Figure 8-3. CPMU Register Summary MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 233: Register Descriptions
NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in Special Mode can alter the S12CPMU_UHV_V11’s functionality. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 234 5. PMRF is set to 1 when a PLL clock monitor reset occurs. Unaffected by System Reset. Cleared by power on reset. = Unimplemented or Reserved Figure 8-6. S12CPMU_UHV_V11 Flags Register (CPMURFLG) Read: Anytime Write: Refer to each bit for individual write conditions MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 235 Figure 8-7. S12CPMU_UHV_V11 Synthesizer Register (CPMUSYNR) Read: Anytime Write: If PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register), then write anytime. Else write has no effect. NOTE Writing to this register clears the LOCK and UPOSC status bits. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 236 Figure 8-8. S12CPMU_UHV_V11 Reference Divider Register (CPMUREFDIV) Read: Anytime Write: If PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register), then write anytime. Else write has no effect. NOTE Write to this register clears the LOCK and UPOSC status bits. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 237 Table 8-4. Reference Clock Frequency Selection if OSC_LCP is enabled REFCLK Frequency Ranges REFFRQ[1:0] (OSCE=1) 1MHz <= f <= 2MHz 2MHz < f <= 6MHz 6MHz < f <= 12MHz >12MHz MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 238 (increases or decreases) f in order to avoid sudden load changes for the on-chip voltage regulator. 8.3.2.7 S12CPMU_UHV_V11 Interrupt Flags Register (CPMUIFLG) This register provides S12CPMU_UHV_V11 status bits and interrupt flags. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 239 Oscillator Status Bit — UPOSC reflects the status of the oscillator. Writes have no effect. Entering Full Stop UPOSC Mode UPOSC is cleared. 0 The oscillator is off or oscillation is not qualified by the PLL. 1 The oscillator is qualified by the PLL. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 240 0 PLL LOCK interrupt requests are disabled. 1 Interrupt will be requested whenever LOCKIF is set. Oscillator Corrupt Interrupt Enable Bit OSCIE 0 Oscillator Corrupt interrupt requests are disabled. 1 Interrupt will be requested whenever OSCIF is set. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 241 (write OMRE = 1 in CPMUOSC2 register). If the oscillator monitor reset feature is disabled (OMRE = 0) and the oscillator clock is used as system clock, the system might stall in case of loss of oscillation. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 242 1 COP continues running during Pseudo Stop Mode if COPOSCSEL=1 Note: If PCE=0 or COPOSCSEL=0 then the COP will go static while Stop Mode is active. The COP counter will not be reset. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 243 UPOSC= 0 clears the COPOSCSEL0 bit. 0 COP clock source is IRCCLK. 1 COP clock source is OSCCLK Table 8-8. COPOSCSEL1, COPOSCSEL0 clock source select description COPOSCSEL1 COPOSCSEL0 COP clock source IRCCLK OSCCLK ACLK MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 244 The modulation frequency is f divided by 16. See Table 8-10 for coding. Table 8-10. FM Amplitude selection FM Amplitude / Variation FM off 1% 2% 4% MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 245 Real Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to RTR[3:0] provide additional granularity.Table 8-12 Table 8-13 show all possible divide values selectable by the CPMURTI register. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 246 1110 (15) 16x2 16x2 16x2 16x2 16x2 16x2 16x2 1111 (16) 1. Denotes the default value out of reset.This value should be used to disable the RTI to ensure future backwards compatibility. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 247 1100 (13) 14x10 28x10 70x10 140x10 280x10 700x10 1.4x10 2.8x10 1101 (14) 15x10 30x10 75x10 150x10 300x10 750x10 1.5x10 3x10 1110 (15) 16x10 32x10 80x10 160x10 320x10 800x10 1.6x10 3.2x10 1111 (16) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 248 2. Writing WCOP bit (anytime in Special Mode, once in Normal Mode) with WRTMASK = 0. 3. Changing RSBCK bit from “0” to “1”. In Special Mode, any write access to CPMUCOP register restarts the COP time-out period. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 249 4) Operation in Special Mode Table 8-15. COP Watchdog Rates if COPOSCSEL1=0. (default out of reset) COPCLK Cycles to time-out (COPCLK is either IRCCLK or OSCCLK depending on the COPOSCSEL0 bit) COP disabled MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 250 Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V11) Table 8-16. COP Watchdog Rates if COPOSCSEL1=1. COPCLK Cycles to time-out (COPCLK is ACLK divided by 2) COP disabled MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 251 Writing to this register when in Special Mode can alter the S12CPMU_UHV_V11’s functionality. Module Base + 0x000E Reset = Unimplemented or Reserved Figure 8-17. Reserved Register (CPMUTEST1) Read: Anytime Write: Only in Special Mode MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 252 ATEMPEN VSEL HTIE HTIF Reset = Unimplemented or Reserved Figure 8-19. High Temperature Control Register (CPMUHTCTL) Read: Anytime Write: ATEMPEN, VSEL, HTE, HTIE and HTIF are write anytime, HTDS is read only MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 253 0 No change in HTDS bit. 1 HTDS bit has changed. NOTE The voltage at the temperature sensor can be computed as follows: (temp) = V - (150 - temp) * dV HT(150) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 254 Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V11) Figure 8-20. Voltage Access Select TEMPSENSE VSEL Channel MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 255 Low-Voltage Interrupt Flag — LVIF is set to 1 when LVDS status bit changes. This flag can only be cleared by LVIF writing a 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request. 0 No change in LVDS bit. 1 LVDS bit has changed. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 256 This flag can only be cleared by writing a 1.Writing a 0 has no effect. If enabled (APIE = 1), APIF causes an interrupt request. 0 API time-out has not yet occurred. 1 API time-out has occurred. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 257 Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V11) Figure 8-23. Waveform selected on API_EXTCLK pin (APIEA=1, APIFE=1) API min. period / 2 APIES=0 API period APIES=1 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 258 ACLK period time. Table 8-21. Trimming Effect of ACLKTR[5:0] ACLKTR[5:0] Decimal ACLK frequency 100000 lowest 100001 increasing ..111111 000000 000001 increasing ..011110 011111 highest MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 259 For APICLK bit clear the first time-out period of the API will show a latency time between two to three f cycles due to synchronous clock ACLK gate release when the API feature gets enabled (APIFE bit set) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 260 12 * Bus Clock period ..FFFD 131068 * Bus Clock period FFFE 131070 * Bus Clock period FFFF 131072 * Bus Clock period 1. When f is trimmed to 20KHz. ACLK MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 261 Writing to this register when in Special Mode can alter the S12CPMU_UHV_V11’s functionality. Module Base + 0x0016 Reset = Unimplemented or Reserved Figure 8-27. Reserved Register (CPMUTEST3) Read: Anytime Write: Only in Special Mode MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 262 HTTR[3:0] Table 8-26. Trimming Effect of HTTR Temperature Interrupt threshold HTTR[3:0] sensor voltage V temperatures T and T HTIA HTID 0000 lowest highest 0001 increasing decreasing ..1110 1111 highest lowest MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 263 0.15%, i.e. 0.3% is the distance between two trimming values). Figure 8-31 shows the relationship between the trim bits and the resulting IRC1M frequency. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 264 Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V11) IRC1M frequency (IRCCLK) IRCTRIM[9:6] 1.5MHz ..IRCTRIM[5:0] 1MHz 600KHz IRCTRIM[9:0] $000 $3FF Figure 8-31. IRC1M Frequency Trimming Diagram MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 265 Setting TCTRIM[4:0] at 0x00000 or 0x10000 does not mean that the temperature coefficient will be zero. These two combinations basically switch off the TC compensation module, which results in the nominal TC of the IRC1M. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 266 NOTE Since the IRC1M frequency is not a linear function of the temperature, but more like a parabola, the above relative variation is only an indication and should be considered with care. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 267 Note: When starting up the external oscillator (either by programming OSCE bit to 1 or on exit from Full Stop Mode with OSCE bit already 1) the software must wait for a minimum time equivalent to the startup-time of the external oscillator t before entering Pseudo Stop Mode. UPOSC MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 268 Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V11) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 269 PROT bit, other write accesses set the PROT bit. 0 Protection of clock and voltage regulator configuration registers is disabled. 1 Protection of clock and voltage regulator configuration registers is enabled. (see list of protected registers above). MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 270 Writing to this register when in Special Mode can alter the S12CPMU_UHV_V11’s functionality. Module Base + 0x001C Reset = Unimplemented or Reserved Figure 8-35. Reserved Register CPMUTEST2 Read: Anytime Write: Only in Special Mode MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 271 Internal voltage regulator Enable Bit for VDDX domain— Should be set to 1 if no external BJT is present on INTXON the PCB, cleared otherwise. 0 VDDX control loop does not use internal power transistor 1 VDDX control loop uses internal power transistor MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 272 If OSCE bit in CPMUOSC register is 1, then the OSCMOD bit can not be changed (writes will have no effect). 0 External oscillator configured for loop controlled mode (reduced amplitude on EXTAL and XTAL)) 1 External oscillator configured for full swing mode (full swing amplitude on EXTAL and XTAL) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 273: Functional Description
If PLL is selected (PLLSEL=1) f bus ------------ - NOTE Although it is possible to set the dividers to command a very high clock frequency, do not exceed the specified bus frequency limit for the MCU. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 274 In case of loss of reference clock (e.g. IRCCLK) the PLL will not lock or if already locked, then it will unlock. The frequency of the VCOCLK will be very low and will depend on the value of the VCOFRQ[1:0] bits. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 275: Startup From Reset
Bus Clock = Core Clock/2 lock LOCK $18 (default target f =50MHz) SYNDIV $03 (default target f /4 = 12.5MHz) POSTDIV example change reset state startup vector fetch, program execution of POSTDIV cycles STARTUP MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 276: Stop Mode Using Pllclk As Source Of The Bus Clock
An example of what happens going into Full Stop Mode and exiting Full Stop Mode after an interrupt is shown in Figure 8-40. Disable PLL Lock interrupt (LOCKIE=0) and oscillator status change interrupt (OSCIE=0) before going into Full Stop Mode. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 277 Stop Mode due to clock domain crossing synchronization. This latency time occurs if COP clock source is ACLK and the CSAD bit is set (please refer to CSAD bit description for details). MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 278: External Oscillator
OSCCLK UPOSC flag is set upon successful start of oscillation UPOSC UPOSC select OSCCLK as Core/Bus Clock by writing PLLSEL to zero PLLSEL based on OSCCLK based on PLL Clock Core Clock MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 279: System Clock Configurations
The PLLCLK is derived from the VCO clock (with its actual frequency) divided by four until the PLL locks again. Application software needs to be prepared to deal with the impact of loosing the oscillator status at any time. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 280: Resets
MCU specification for reset vector address. Table 8-34. Reset Summary Reset Source Local Enable Power-On Reset (POR) None Low Voltage Reset (LVR) None External pin RESET None PLL Clock Monitor Reset None MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 281: Description Of Reset Operation
CMFA (see device electrical characteristics for values), the S12CPMU_UHV_V11 generates an Oscillator Clock Monitor Reset. In Full Stop Mode the external oscillator and the oscillator clock monitor are disabled. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 282: Pll Clock Monitor Reset
OSCE UPOSC (clock source) Run (ACLK) Static (ACLK) Run (OSCCLK) Static (IRCCLK) Static (IRCCLK) Static (IRCCLK) Static (OSCCLK) Static (OSCCLK) Static (IRCCLK) Static (IRCCLK) Satic (OSCCLK) Static (IRCCLK) Static (IRCCLK) Static (IRCCLK) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 283: Power-On Reset (Por)
The LVR assert and deassert levels for the supply voltage VDDX are V and V and are LVRXA LVRXD specified in the device Reference Manual.The LVR circuitry is active in Run- and Wait Mode. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 284: Interrupts
0 by writing a 1 to the LOCKIF bit. 8.6.1.3 Oscillator Status Interrupt When the OSCE bit is 0, then UPOSC stays 0. When OSCE=1 the UPOSC bit is set after the LOCK bit is set. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 285 The API Trimming bits ACLKTR[5:0] must be set so the minimum period equals 0.2 ms if stable frequency is desired. Table 8-21 for the trimming effect of ACLKTR[5:0]. 1. For details please refer to “8.4.6 System Clock Configurations” MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 286: Initialization/Application Information
If the COP is stopped during any Stop Mode it is recommended to service the COP shortly before Stop Mode is entered. 8.7.3 Application Information for PLL and Oscillator Startup The following C-code example shows a recommended way of setting up the system clock system using the PLL and Oscillator: MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 287 /* put your code to loop and wait for the LOCKIF or */ /* poll CPMUIFLG register until both LOCK status is “1” */ /* that is CPMIFLG == 0x18 */ /*....continue to your main code execution here....*/ MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 288 Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V11) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 289: Differences Adc12B_Lba V1 Vs V2 Vs V3
Chapter 9 Analog-to-Digital Converter Table 9-1. Revision History Revision Revision Sections Affected Description of Changes Number Date V1.37 19. Apr 2013 Updates from review of reference manual to fix typos etc. Provided more detailed information regarding captured information in V1.38 30.
Page 290: Introduction
(see device level specification for more details). DISABLE MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 291: Key Features
• Four option bits in the conversion command for top level SoC specific feature/function implementation option (Please refer to the device reference manual for details of the top level feature/function if implemented) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 292: Modes Of Operation
— The RVL buffer select (RVL_SEL) is not changed if a CSL is in process at MCU Stop Mode request. Hence the same buffer will be used after exit from Stop Mode that was used when the Stop Mode request occurred. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 293 — The RVL buffer select (RVL_SEL) is not changed if a CSL is in process at MCU Wait Mode request. Hence the same RVL buffer will be used after exit from Wait Mode that was used when Wait Mode request occurred. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 294 Freeze Mode is entered. After exit from MCU Freeze Mode with previously frozen conversion sequence the ADC continues the conversion with the next conversion command and all ADC interrupt flags are unchanged during MCU Freeze Mode. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 295: Block Diagram
Register (SAR) ... VRL_0 Alternative and C-DAC ... Result ... List ... VDDA (RAM) Result 63 VSSA Final ..Buffer ext. Buffer Comparator Channel Sample & Hold ADC10B_LBA Figure 9-2. ADC12B_LBA Block Diagram MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 296: Signal Description
VRH_2 is only available on ADC12B_LBA V3. VRL_1 is only available on ADC12B_LBA V1 and V2. See also Table 9-2. 9.4.1.3 VDDA, VSSA These pins are the power supplies for the analog circuitry of the ADC12B_LBA block. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 297: Memory Map And Register Definition
0x000B ADCCONIE_1 CON_IE[7:1] EOL_IE 0x000C ADCCONIF_0 CON_IF[15:8] 0x000D ADCCONIF_1 CON_IF[7:1] EOL_IF R CSL_IMD RVL_IMD 0x000E ADCIMDRI_0 RIDX_IMD[5:0] 0x000F ADCIMDRI_1 = Unimplemented or Reserved Figure 9-3. ADC12B_LBA Register Summary (Sheet 1 of 3) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 298 CMD_PTR[23:16] 0x001E ADCCBP_1 CMD_PTR[15:8] 0x001F ADCCBP_2 CMD_PTR[7:2] RES_IDX[5:0] 0x0020 ADCRIDX 0x0021 ADCRBP_0 RES_PTR[19:16] 0x0022 ADCRBP_1 RES_PTR[15:8] 0x0023 ADCRBP_2 RES_PTR[7:2] = Unimplemented or Reserved Figure 9-3. ADC12B_LBA Register Summary (Sheet 2 of 3) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 299 ADCCROFF1 CMDRES_OFF1[6:0] 0x0026 Reserved Reserved 0x0027 Reserved Reserved 0x0028 Reserved Reserved R Reserved Reserved 0x0029 Reserved 0x002A- Reserved 0x003F = Unimplemented or Reserved Figure 9-3. ADC12B_LBA Register Summary (Sheet 3 of 3) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 300: Register Descriptions
ADC freezes the conversion at next conversion boundary at Freeze Mode entry. Wait Mode Configuration — This bit influences conversion flow during Wait Mode. SWAI ADC continues conversion in Wait Mode. ADC halts the conversion at next conversion boundary at Wait Mode entry. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 301 Each conversion flow control bit (SEQA, RSTA, TRIG, LDOK) must be controlled by software or internal interface according to the requirements described in Section 9.6.3.2.4, “The two conversion flow control Mode Configurations and overview summary in Table 9-11. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 302 ADC conversion flow control mode “Trigger Mode” and “Restart Mode” (anytime during application runtime). No automatic Restart Event after exit from MCU Stop Mode. 1 Automatic Restart Event occurs after exit from MCU Stop Mode. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 303 Sequence Abort Event after exit from MCU Wait Mode (see also the Note in Section 9.3.1.2, “MCU Operating Modes). 0 ADC not in idle state. 1 ADC is in idle state. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 304 ADC Clock Prescaler — These 7bits are the binary prescaler value PRS. The ADC conversion clock frequency PRS[6:0] is calculated as follows: f BUS ----------------------------------- -   Refer to Device Specification for allowed frequency range of f ATDCLK MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 305 1. This reserved setting causes a severe error at ADC conversion start whereby the CMD_EIF flag is set and ADC ceases operation 2. This reserved setting does not cause an error; CMD_EIF is not set MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 306 Bus Clock cycles plus an uncertainty of a few Bus Clock cycles. For more details regarding the sample phase please refer to Section 9.6.2.2, “Sample and Hold Machine with Sample Buffer Amplifier. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 307 This bit can be controlled via the internal interface Signal “Trigger” if access control is configured accordingly via ACC_CFG[1:0]. After being set an additional request via internal interface Signal “Trigger“ causes the flag TRIG_EIF to be set. 0 No conversion sequence trigger. 1 Trigger to start conversion sequence. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 308 The LDOK_EIF error flag is also not set in “Restart Mode” if the first Restart Event occurs after: - ADC got enabled - Exit from Stop Mode - ADC Soft-Reset 0 Load of alternative list done. 1 Load alternative list. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 309 Section 9.6.3.2.4, “The two conversion flow control Mode Configurations, Section 9.6.3.2.5, “The four ADC conversion flow control bits Section 9.6.3.2.6, “Conversion flow control in case of conversion sequence control bit overrun scenarios MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 310 1 Restart Request error interrupt enabled. Load OK Error Interrupt Enable Bit — This bit enables the Load OK error interrupt. LDOK_EIE 0 Load OK error interrupt disabled. 1 Load OK error interrupt enabled. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 311 ADCCONIF Register Flags Overrun Interrupt Enable — This bit enables the flag which indicates if an overrun CONIF_OIE situation occurred for one of the CON_IF[15:1] flags or for the EOL_IF flag. 0 No ADCCONIF Register Flag overrun occurred. 1 ADCCONIF Register Flag overrun occurred. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 312 CSL. The ADC ceases operation if this error flag is set (issue of type severe). 0 No “End Of List” error. 1 “End Of List” command type missing in current executed CSL. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 313 - ADC Soft-Reset - ADC used in CSL single buffer mode The ADC continues operation if this error flag is set. 0 No Load OK error situation occurred. 1 Load OK error situation occurred. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 314 The overrun is detected if any of the conversion interrupt flags (CON_IF[15:1]) is set while the first conversion result of a CSL is stored (result of first conversion from top of CSL is stored). MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 315 1 ADC conversion interrupt enabled. End Of List Interrupt Enable Bit — This bit enables the end of conversion sequence list interrupt. EOL_IE 0 End of list interrupt disabled. 1 End of list interrupt enabled. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 316 (see also Section 9.9.6, “RVL swapping in RVL double buffer mode and related registers ADCIMDRI and ADCEOLRI. NOTE Overrun situation of a flag CON_IF[15:1] and EOL_IF are indicated by flag CONIF_OIF. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 317 In case a Sequence Abort Event was initiated by hardware due to MCU entering Stop Mode or Wait Mode with bit SWAI set, the result index of the last stored result is captured by bits RIDX_IMD but flag SEQAD_IF is not set. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 318 The register ADCIMDRI is updated and simultaneously a conversion interrupt flag CON_IF[15:1] occurs when the corresponding conversion command (conversion command with INTFLG_SEL[3:0] set) has been processed and related data has been stored to RAM. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 319 NOTE The conversion interrupt EOL_IF occurs and simultaneously the register ADCEOLRI is updated when the “End Of List” conversion command type has been processed and related data has been stored to RAM. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 320 Table 9-21. Conversion Command Type Select CMD_SEL[1] CMD_SEL[0] Conversion Command Type Description Normal Conversion End Of Sequence (Wait for Trigger to execute next sequence or for a Restart) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 321 Continue Conversion) End Of List (Wrap to top of CSL and: - In “Restart Mode” wait for Restart Event followed by a Trigger - In “Trigger Mode” wait for Trigger or Restart Event) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 322 Table 9-22. Conversion Interrupt Flag Select CON_IF[15:1] INTFLG_SEL[3] INTFLG_SEL[2] INTFLG_SEL[1] INTFLG_SEL[0] Comment 0x0000 No flag set 0x0001 Only one flag can be set 0x0002 (one hot coding) 0x0004 0x0008 0x0010 ..0x0800 0x1000 0x2000 0x4000 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 323 ADC Input Channel Select Bits — These bits select the input channel for the current conversion. See Table 9- CH_SEL[5:0] for channel coding information. NOTE If bit SMOD_ACC is set modifying this register must be done carefully - only when no conversion and conversion sequence is ongoing. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 324 Table 9-24 is the maximum number of implemented analog input channels on the device. Please refer to the device overview of the reference manual for details regarding number of analog input channels. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 325 If bit SMOD_ACC is set modifying this register must be done carefully - only when no conversion and conversion sequence is ongoing. Table 9-26. Sample Time Select SMP[4] SMP[3] SMP[2] SMP[1] SMP[0] Sample Time in Number of ADC Clock Cycles MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 326 Chapter 9 Analog-to-Digital Converter Table 9-26. Sample Time Select SMP[4] SMP[3] SMP[2] SMP[1] SMP[0] Sample Time in Number of ADC Clock Cycles Reserved Reserved Reserved Reserved MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 327 Chapter 9 Analog-to-Digital Converter 9.5.2.18 ADC Command Register 3 (ADCCMD_3) Module Base + 0x0017 Reserved Reserved Reserved Reset = Unimplemented or Reserved Figure 9-21. ADC Command Register 3 (ADCCMD_3) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 328 CSL start addresses in the memory map. These bits do not represent absolute addresses [5:0] instead it is a sample index (object size 32bit). See also Section 9.6.3.2.2, “Introduction of the two Command Sequence Lists (CSLs) for more details. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 329 RAM or NVM of the memory map. They are used to calculate the final address from which the [23:2] conversion commands will be loaded depending on which list is active. For more details see Section 9.6.3.2.2, “Introduction of the two Command Sequence Lists (CSLs). MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 330 RVL start addresses in the memory map. These bits do not represent absolute addresses instead it is a sample index (object size 16bit). See also Section 9.6.3.2.3, “Introduction of the two Result Value Lists (RVLs) for more details. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 331 RAM of the memory map to which conversion results will be stored to at the end of a conversion. These bits can only be written if bit ADC_EN is clear. See also Section 9.6.3.2.3, “Introduction of the two Result Value Lists (RVLs). MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 332 (object size 16bit for RVL, object size 32bit for CSL). See also Section 9.6.3.2.2, “Introduction of the two Command Sequence Lists (CSLs) Section 9.6.3.2.3, “Introduction of the two Result Value Lists (RVLs) for more details. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 333 (object size 16bit for RVL, object size 32bit for CSL).,These bits can only be modified if bit ADC_EN is clear. See also Section 9.6.3.2.2, “Introduction of the two Command Sequence Lists (CSLs) Section 9.6.3.2.3, “Introduction of the two Result Value Lists (RVLs) for more details. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 334: Functional Description
Appendix of the device reference manual for more details. The input analog signals are unipolar and must be within the potential range of VSSA to VDDA. During the hold process, the analog input is disconnected from the storage node. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 335: Digital Sub-Block
(bits CSL_BMOD, RVL_BMOD). The 32-bit wide conversion command is double buffered and the currently active command is visible in the ADC register map at ADCCMD register space. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 336 Command_11 normal conversion to proceed Sequence_3 Command_12 normal conversion Wait for RSTA or LDOK+RSTA Command_13 End Of List Figure 9-29. Example CSL with sequences and an “End Of List” command type identifier MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 337 Command_8 normal conversion Command_9 normal conversion Command_10 normal conversion Command_11 normal conversion Command_12 normal conversion Command_13 End Of List, wrap to top, continue Figure 9-30. Example CSL for continues conversion MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 338 RAM or NVM end address Note: Address register names in () are not absolute addresses instead they are a sample offset or sample index Figure 9-31. Command Sequence List Schema in Double Buffer Mode MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 339 CSL double buffered mode. When the ADC is enabled, the command address registers (ADCCBP, ADCCROFF_0/2, ADCCIDX) are read only and register ADCCIDX is under control of the ADC. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 340 RAM end address Note: Address register names in () are not absolute addresses instead they are a sample offset or sample index Figure 9-33. Result Value List Schema in Double Buffer Mode MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 341 DJM control bit. Unused bits inside an entity are stored zero. Table 9-33. Conversion Result Justification Overview Conversion Resolution Left Justified Result Right Justified Result (SRES[1:0]) (DJM = 1’b0) (DJM = 1’b1) 8 bit {Result[7:0],8’b00000000} {8’b00000000,Result[7:0]} 10 bit {Result[9:0],6’b000000} {6’b000000,Result[9:0]} MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 342 Table 9-11. • Trigger Event Internal Interface Signal: Trigger Corresponding Bit Name: TRIG – Function: Start the first conversion of a conversion sequence which is defined in the active Command Sequence List MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 343 This bit is cleared when the first conversion command of the sequence from top of active Sequence Command List is loaded – Mandatory Requirement: - In all ADC conversion flow control modes a Restart Event causes bit RSTA to be set. Bit MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 344 CSL at the next Trigger Event (no exchange of CSL list). If signal Restart is asserted after or simultaneously with signal LoadOK the conversion starts from top of the other CSL at the next Trigger Event (CSL is switched) if CSL is MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 345 * A Sequence Abort request is about to be executed or has been executed. In case bit SEQA is set automatically the Restart error flag RSTA_EIF is set to indicate an unexpected Restart Request. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 346 Sequence Abort Request Overrun: If a Sequence Abort Request occurs whilst bit SEQA is already set, this is defined as a Sequence Abort Request Overrun situation and the overrun request is ignored. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 347 Trigger Event to continue. • If the last executed conversion command was of type “Normal Conversion” the ADC continues command execution in the order of the current CSL (continues conversion). MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 348: Resets
The ADC provides one sequence abort done interrupt associated with the sequence abort request for conversion flow control. Hence, there is only one dedicated interrupt flag and interrupt enable bit for conversion sequence abort and it occurs when the sequence abort is done. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 349: Adc Error And Conversion Flow Control Issue Interrupt
In order to make the ADC operational again an ADC Soft-Reset must be issued. Remaining error interrupt flags cause an error interrupt if enabled, but ADC continues operation. The related interrupt flags are: • RSTAR_EIF • LDOK_EIF • CONIF_OIF MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 350: Use Cases And Application Information
The last entirely filled RVL (an RVL where the corresponding CSL has been executed including the “End Of List “ command type) is shown by register ADCEOLRI. The CSL is used in single buffer mode and bit CSL_SEL is forced to 1’b0. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 351: List Usage — Csl Double Buffer Mode And Rvl Double Buffer Mode
Command Sequence List is reached, if bits LDOK and RSTA are set, the commands list is swapped. CSL_0 RVL_0 RVL_1 CSL_1 (unused) Figure 9-38. CSL Double Buffer Mode — RVL Single Buffer Mode Diagram MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 352: List Usage — Csl Double Buffer Mode And Rvl Double Buffer Mode
Hence application software can pick up conversion results, or groups of results, or an entire result list driven fully by interrupts. A use case example diagram is shown in Figure 9-40. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 353 One of the CON_IF interrupt flags occurs Delay can vary depending on the DMA performance, and ADC configuration (conversion delay flow using the Trigger to proceed through the CSL) Figure 9-40. RVL Swapping — Use Case Diagram MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 354: Conversion Flow Control Application Information
After the Restart Event is finished (bit RSTA is cleared), the ADC accepts a new Trigger Event (bit TRIG can be set) and begins conversion from the top of the currently active CSL. In conversion flow control MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 355 If only a Restart Event occurs while ADC is not idle and bit SEQA is not set already (Sequence Abort Event in progress) a Sequence Abort Event is issued automatically and bit RSTAR_EIF is set. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 356: Continuous Conversion
AN3 AN1 AN4 IN5 AN3 AN1 AN4 IN5 AN3 AN1 AN3 AN1 AN4 Stop Mode entry Abort Active CSL_0 Active Idle Idle Figure 9-41. Conversion Flow Control Diagram — Continuous Conversion (with Stop Mode) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 357: Triggered Conversion — Single Csl
If bit AUT_RSTA is set before Low Power Mode is entered, the conversion continues automatically as soon as a low power mode (Stop Mode or Wait Mode with bit SWAI set) is exited. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 358: Fully Timing Controlled Conversion
Fully Timing Controlled Conversion) can be used with CSL single buffer mode or with CSL double buffer mode. If using CSL double buffer mode, CSL swapping is performed by issuing a Restart Event with bit LDOK set. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 359: Introduction
Chapter 10 Supply Voltage Sensor - (BATSV3) Table 10-1. Revision History Table Rev. No. Data Sections Substantial Change(s) (Item No.) Affected V01.00 15 Dec 2010 Initial Version V02.00 16 Mar 2011 10.3.2.1 - added BVLS[1] to support four voltage level 10.4.2.1 - moved BVHS to register bit 6 V03.00...
Page 360: Block Diagram
This pin is the chip supply. It can be internally connected for voltage measurement. The voltage present at this input is scaled down by an internal voltage divider, and can be routed to the internal ADC or to a comparator. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 361: Memory Map And Register Definition
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. Unused bits read back zero. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 362 + two bus cycles the measured value is invalid. EN_UNC This is to let internal nodes be charged to correct value. BVHIE, BVLIE might be cleared for this time period to avoid false interrupts. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 363 V (falling edge) or V (rising edge) measured LBI_A measured LBI_D V V (falling edge) or V (rising edge) measured LBI_A measured LBI_D Figure 10-5. BATS Voltage Sensing HBI_A HBI_D LBI_D LBI_A MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 364 BATS Interrupt Flag Register (BATIF) 10.3.2.4 Module Base + 0x0003 Access: User read/write BVHIF BVLIF Reset = Unimplemented Figure 10-7. BATS Interrupt Flag Register (BATIF) 1. Read: Anytime Write: Anytime, write 1 to clear MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 365: Functional Description
Entering and exiting CPU stop mode has no effect on the interrupt flags. To make sure the interrupt generation works properly the bus clock frequency must be higher than the Voltage Warning Low Pass Filter frequency (f VWLP_filter MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 366 BVLIF can only be cleared by writing a 1. If the interrupt is enabled by bit BVLIE the module requests an interrupt to MCU (BATI). 10.4.2.2 BATS Voltage High Condition Interrupt (BVHI) To use the Voltage High Interrupt the Level Sensing must be enabled (BSUSE=1). MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 367 Interrupt flag (BVHIF) is set to 1 when a Voltage High Condition (BVHC) changes state. The Interrupt flag BVHIF can only be cleared by writing a 1. If the interrupt is enabled by bit BVHIE the module requests an interrupt to MCU (BATI). MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 368 Chapter 10 Supply Voltage Sensor - (BATSV3) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 369: Introduction
Chapter 11 Timer Module (TIM16B4CV3) Block Description Table 11-1. V03.02 Apri,12,2010 11.3.2.9/11-378 -update TCRE bit description 11.4.3/11-385 V03.03 Jan,14,2013 -single source generate different channel guide 11.1 Introduction The basic scalable timer consists of a 16-bit, software-programmable counter driven by a flexible programmable prescaler.
Page 370: Block Diagrams
Timer channel 2 IOC3 Output compare interrupt Timer channel 3 interrupt Figure 11-1. TIM16B4CV3 Block Diagram 16-bit Main Timer IOCn Edge detector Set CnF Interrupt TCn Input Capture Reg. Figure 11-2. Interrupt Flag Setting MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 371: External Signal Description
TSCR1 0x0007 R RESERV RESERV RESERV RESERV TOV3 TOV2 TOV1 TOV0 TTOV 0x0008 R RESERV RESERV RESERV RESERV RESERV RESERV RESERV RESERV TCTL1 Figure 11-3. TIM16B4CV3 Register Summary (Sheet 1 of 2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 372 11.3.2.1 Timer Input Capture/Output Compare Select (TIOS) Module Base + 0x0000 RESERVED RESERVED RESERVED RESERVED IOS3 IOS2 IOS1 IOS0 Reset Figure 11-4. Timer Input Capture/Output Compare Select (TIOS) Read: Anytime Write: Anytime MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 373 11.3.2.3 Timer Count Register (TCNT) Module Base + 0x0004 TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8 Reset Figure 11-6. Timer Count Register High (TCNTH) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 374 0 Allows the timer module to continue running during wait. 1 Disables the timer module when the MCU is in the wait mode. Timer interrupts cannot be used to get the MCU out of wait. TSWAI also affects pulse accumulator. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 375 TOV[3:0] in output compare mode. When set, it takes precedence over forced output compare 0 Toggle output compare pin on overflow feature disabled. 1 Toggle output compare pin on overflow feature enabled. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 376 Table 11-7. Compare Result Output Action Action No output compare action on the timer output signal Toggle OCx output line Clear OCx output line to zero Set OCx output line to one MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 377 Input Capture Edge Control — These four pairs of control bits configure the input capture edge detector EDGnB circuits. EDGnA Table 11-9. Edge Detector Circuit Configuration EDGnB EDGnA Configuration Capture disabled Capture on rising edges only Capture on falling edges only Capture on any edge (rising or falling) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 378 1 Hardware interrupt requested when TOF flag set. Timer Prescaler Select — These three bits select the frequency of the timer prescaler clock derived from the PR[2:0] Bus Clock as shown in Table 11-12. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 379 Note: When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare channel (0x0010–0x001F) will cause the corresponding channel flag CxF to be cleared. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 380 Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000. Clearing this bit requires writing a one to bit 7 of TFLG2 register while the TEN bit of TSCR1 is set to one . MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 381 All timer input capture/output compare registers are reset to 0x0000. NOTE Read/Write access in byte mode for high byte should take place before low byte otherwise it will give a different result. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 382 11.3.2.14 Precision Timer Prescaler Select Register (PTPSR) Module Base + 0x002E PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 Reset Figure 11-21. Precision Timer Prescaler Select Register (PTPSR) Read: Anytime Write: Anytime All bits reset to zero. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 383: Functional Description
PTPS2 PTPS1 PTPS0 Factor 11.4 Functional Description This section provides a complete functional description of the timer TIM16B4CV3 block. Please refer to the detailed timer block diagram in Figure 11-22 as necessary. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 384: Prescaler
2 (TSCR2) are set to define a prescalar value that generates a divide by 1, 2, 4, 8, 16, 32, 64 and 128 when the PRNT bit in TSCR1 is disabled. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 385: Input Capture
OCPDx and TEN bits set to one. Set OCx: Write a 1 to FOCx while TEN=1, IOSx=1, OMx=1, OLx=1 and OCPDx=1 Clear OCx: Write a 1 to FOCx while TEN=1, IOSx=1, OMx=1, OLx=0 and OCPDx=1 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 386: Resets
Timer Overflow Interrupt (TOF) This active high output will be asserted by the module to request a timer overflow interrupt. The TIM block only generates the interrupt and does not service it. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 387: Chapter 12
Chapter 12 Pulse Width Modulator with Fault Protection (PMF15B6CV4) Table 12-1. Revision History Rev. No. Date Sections Substantial Change(s) (Item No.) (Submitted By) Affected V03.22 02 Sep 2013 12.3.2.4/12-401 • Corrected PINVx bit descriptions 12.3.2.11/12-406 • Improved read description of PMFOUTB V03.23 10 Oct 2013 12.2.8/12-392...
Page 388: Introduction
All PWM outputs can be generated from the same counter, or each pair can have its own counter for three independent PWM frequencies. Complementary operation permits programmable deadtime insertion, distortion correction through current sensing by software, and separate top and bottom output polarity MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 389: Features
Table 12-4. Modes When PWM Operation is Restricted Mode Description STOP PWM outputs are disabled WAIT PWM outputs are disabled as a function of the PMFWAI bit FREEZE PWM outputs are disabled as a function of the PMFFRZ bit MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 390: Block Diagram
RELOAD C INTERRUPT REQUEST FIF2 QSMP2 FIE0-5 INTERRUPT FAULT0-5 INTERRUPT REQUEST CONTROL FIF3 QSMP3 FIF0-5 FIF4 QSMP4 PMFROIE FIF5 QSMP5 PMFROIF RELOAD OVERRUN A or B or C INTERRUPT REQUEST Figure 12-1. PMF Block Diagram MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 391: Signal Descriptions
(preferably timer output compare channel) at integration level. The commutation event input must be enabled to take effect (ENCE=1). When this bit is set the PMFOUTC, PMFOUT, and MSKx registers switch from non-buffered to async_event triggered double MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 392: Commutation Event Edge Select Signal — Async_Event_Edge_Sel[1:0]
Whenever the async_event signal causes pmf_reloada output to assert also the pmf_reload_is_async output asserts for the same duration, except if asynchronous event and generated PWM reload event occur in the same cycle. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 393: Memory Map And Registers
FIF3 FIF2 FIF1 FIF0 0x0008 PMFQSMP0 QSMP5 QSMP4 0x0009 PMFQSMP1 QSMP3 QSMP2 QSMP1 QSMP0 0x000A- Reserved 0x000B = Unimplemented or Reserved Figure 12-2. Quick Reference to PMF Registers (Sheet 1 of 5) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 394 PMFVAL2 PMFVAL2 0x0016 PMFVAL3 PMFVAL3 0x0017 PMFVAL3 PMFVAL3 0x0018 PMFVAL4 PMFVAL4 0x0019 PMFVAL4 PMFVAL4 0x001A PMFVAL5 PMFVAL5 = Unimplemented or Reserved Figure 12-2. Quick Reference to PMF Registers (Sheet 2 of 5) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 395 PMFDTMA 0x0027 PMFDTMA PMFDTMA 0x0028 PMFENCB PWMENB GLDOKB RSTRTB LDOKB PWMRIEB 0x0029 PMFFQCB LDFQB HALFB PRSCB PWMRFB = Unimplemented or Reserved Figure 12-2. Quick Reference to PMF Registers (Sheet 3 of 5) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 396 PMFDTMB 0x002F PMFDTMB PMFDTMB 0x0030 PMFENCC PWMENC GLDOKC RSTRTC LDOKC PWMRIEC 0x0031 PMFFQCC LDFQC HALFC PRSCC PWMRFC = Unimplemented or Reserved Figure 12-2. Quick Reference to PMF Registers (Sheet 4 of 5) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 397 PMFDMP5 DMP55 DMP54 DMP53 DMP52 DMP51 DMP50 0x003E PMFOUTF OUTF5 OUTF4 OUTF3 OUTF2 OUTF1 OUTF0 0x003F Reserved = Unimplemented or Reserved Figure 12-2. Quick Reference to PMF Registers (Sheet 5 of 5) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 398: Register Descriptions
PWMs or complementary PWMs. This bit cannot be modified after the WP bit is set. 0 PWM4 and PWM5 are complementary PWM pair 1 PWM4 and PWM5 are independent PWMs MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 399 Pair C Bottom-Side PWM Polarity — This bit determines the polarity for Pair C bottom-side PWM (PWM5). This BOTNEGC bit cannot be modified after the WP bit is set. 0 Positive PWM5 polarity 1 Negative PWM5 polarity MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 400 This register cannot be modified after the WP bit is set. 00 Reload event generation disabled 01 PWM generator A generates reload event 10 PWM generator B generates reload event 11 PWM generator C generates reload event MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 401 PWM registers. This bit cannot be modified after the WP bit is set. 0 PMF continues to run in FREEZE mode 1 PMF is disabled in FREEZE mode MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 402 Access: User read/write FEN5 FEN4 FEN3 FEN2 FEN1 FEN0 Reset Figure 12-7. PMF Fault Enable Register (PMFFEN) 1. Read: Anytime Write: This register cannot be modified after the WP bit is set MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 403 PMF Fault Interrupt Enable Register (PMFFIE) Address: Module Base + 0x0006 Access: User read/write FIE5 FIE4 FIE3 FIE2 FIE1 FIE0 Reset Figure 12-9. PMF Fault Interrupt Enable Register (PMFFIE) 1. Read: Anytime Write: Anytime MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 404 Address: Module Base + 0x0008 Access: User read/write QSMP5 QSMP4 Reset Figure 12-11. PMF Fault Qualifying Samples Register (PMFQSMP0) 1. Read: Anytime Write: This register cannot be modified after the WP bit is set. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 405 12.3.2.10 PMF Output Control Register (PMFOUTC) Address: Module Base + 0x000C Access: User read/write OUTCTL5 OUTCTL4 OUTCTL3 OUTCTL2 OUTCTL1 OUTCTL0 Reset Figure 12-13. PMF Output Control Register (PMFOUTC) 1. Read: Anytime Write: Anytime MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 406 Table 12-18. Software Output Control Complementary Independent OUTn Bit Channel Operation Channel Operation OUT0 1 — PWM0 is active 1 — PWM0 is active 0 — PWM0 is inactive 0 — PWM0 is inactive MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 407 0, 1, 2, 3, 4 and 5. 12.3.2.13 PMF Correction Control Register (PMFCCTL) Address: Module Base + 0x000F Access: User read/write ISENS IPOLC IPOLB IPOLA Reset Figure 12-16. PMF Correction Control Register (PMFCCTL) 1. Read: Anytime Write: Anytime MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 408 01 to the current select bits, ISENS[1:0], in the PWM control register. Reading the IPOLx bits read the buffered value and not necessarily the value currently in effect. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 409 Figure 12-18. PMF Interrupt Enable Register (PMFROIE) 1. Read: Anytime Write: Anytime Table 12-23. PMFROIE Descriptions Field Description Reload Overrun Interrupt Enable C — PMFROIEC 0 Reload Overrun Interrupt C disabled 1 Reload Overrun Interrupt C enabled MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 410 If PMFCFG2[REV1:REV0]=11 and a reload event occurs when the LDOKC or global load OK bit is not set then this flag will be set. If PMFCFG2[REV1:REV0]=00 no flag will be generated. 0 No Reload Overrun A occurred 1 Reload Overrun A occurred MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 411 Pulse Edge Control — This bit controls PWM0/PWM1 pair. PECA 0 Normal operation 1 Allow one of PMFVAL0 and PMFVAL1 to activate the PWM pulse and the other to deactivate the pulse MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 412 Figure 12-43. 0 PWM output 2 is high when PMFCNTB (PMFCNTA if MTG=0) is less than PMFVAL2 1 PWM output 2 is high when PMFCNTB (PMFCNTA if MTG=0) is greater than PMFVAL2 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 413 This bit cannot be modified after the WP bit is set. 0 No PWM generator A restart at the next commutation event. 1 PWM generator A restarts at the next commutation event MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 414 PWMs. It takes effect immediately. When set, reload opportunities occur also when the counter matches the modulus in addition to the start of the PWM period at count zero. See Section 12.4.12.3, “Load Frequency” for more details. 0 Half-cycle reloads disabled 1 Half-cycle reloads enabled MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 415 Address: Module Base + 0x0022 Access: User read/write PMFCNTA Reset Figure 12-26. PMF Counter A Register (PMFCNTA) 1. Read: Anytime Write: Never This register displays the state of the 15-bit PWM A counter. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 416 DEAD_A PWM_A core 12.3.2.24 PMF Enable Control B Register (PMFENCB) Address: Module Base + 0x0028 Access: User read/write PWMENB GLDOKB RSTRTB LDOKB PWMRIEB Reset Figure 12-29. PMF Enable Control B Register (PMFENCB) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 417 Address: Module Base + 0x0029 Access: User read/write LDFQB HALFB PRSCB PWMRFB Reset Figure 12-30. PMF Frequency Control B Register (PMFFQCB) 1. Read: Anytime. Returns zero if MTG is clear. Write: Anytime if MTG is set. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 418 Every 15 PWM opportunities 0111 Every 8 PWM opportunities 1111 Every 16 PWM opportunities Table 12-32. PWM Prescaler B PRSCB[1:0] Prescaler Value P PWM Clock Frequency f PWM_B core core core core MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 419 The 12-bit value written to this register is the number of PWM clock cycles in complementary channel operation. A reset sets the PWM deadtime register to the maximum value of 0x0FFF, selecting a deadtime MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 420 1 Load prescaler C, modulus C, and PWM4–5 values Note: Do not set PWMENC bit before setting the LDOKC bit and do not clear the LDOKC bit at the same time as setting the PWMENC bit. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 421 PWMRFC bit. If another reload occurs before the clearing sequence is complete, writing logic one to PWMRFC has no effect. 0 No new reload cycle since last PWMRFC clearing 1 New reload cycle since last PWMRFC clearing Note: Clearing PWMRFC satisfies pending PWMRFC CPU interrupt requests. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 422 Write: Anytime if MTG is set. Do not write a modulus value of zero for center-aligned operation. Do not write a modulus of zero or one in edge-aligned mode. The 15-bit unsigned value written to this register is the PWM period in PWM clock periods. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 423 Module Base + 0x003D PMFDMP5 DMPn5 DMPn4 DMPn3 DMPn2 DMPn1 DMPn0 Reset Figure 12-39. PMF Disable Mapping Register (PMFDMP0-5) 1. Read: Anytime Write: This register cannot be modified after the WP bit is set. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 424 OUTF Bits — When the corresponding DMPn4 or DMPn5 bits are set to switch to output control on a related OUTF[5:0] FAULT4 or FAULT5 event, these bits control the PWM outputs, illustrated in Table 12-39.This register cannot be modified after the WP bit is set. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 425 0 — PWM4 is inactive 0 — PWM4 is inactive OUTF5 1 — PWM5 is complement of PWM4 1 — PWM5 is active 0 — PWM5 is inactive 0 — PWM5 is inactive MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 426: Functional Description
Section 12.3.2.2, “PMF Configure 1 Register (PMFCFG1)” for the description of TOPNEG and BOTNEG bits, and Section 12.3.2.3, “PMF Configure 2 Register (PMFCFG2)” for the description of the MSK0 and MSK1 bits. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 427: Prescaler
PWM counter, and PWM counter is counting upwards if the corresponding channel CINVn=0. Or, the PWM compare output is driven to high state if the corresponding channel CINVn=1. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 428 PWM period = (PWM modulus) (PWM clock period)  2 Eqn. 12-4 COUNTER UP/DOWN COUNTERER MODULUS = 4 PWM CLOCK PERIOD PWM PERIOD = 8 x PWM CLOCK PERIOD Figure 12-44. Center-Aligned PWM Period MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 429 A PWM value less than or equal to zero deactivates the PWM output for the entire PWM period. A PWM value greater than or equal to the modulus activates the PWM output for the entire PWM period when CINVn=0, and vice versa if CINVn=1. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 430 PWM VALUE = 4 4/4 = 100% Figure 12-46. Center-Aligned PWM Pulse Width Edge-aligned operation is illustrated in Figure 12-47. PWM pulse width = (PWM value)  (PWM clock period) Eqn. 12-7 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 431: Independent Or Complementary Channel Operation
PWM CHANNELS 0 AND 1 BOTTOM PMFVAL2 PMFVAL3 REGISTER REGISTER PAIR B PWM CHANNELS 2 AND 3 BOTTOM PMFVAL4 PMFVAL5 REGISTER REGISTER PAIR C PWM CHANNELS 4 AND 5 BOTTOM Figure 12-48. Complementary Channel Pairs MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 432: Deadtime Generators
Every time the deadtime generator inputs changes state, deadtime is inserted. Deadtime forces both PWM outputs in the pair to the inactive state. A method of correcting this, adding to or subtracting from the PWM value used, is discussed next. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 433 OUTCTL4 Figure 12-50. Deadtime Generators MODULUS = 4 PWM VALUE = 2 PWM0, NO DEADTIME PWM1, NO DEADTIME PWM0, DEADTIME = 1 PWM1, DEADTIME = 1 Figure 12-51. Deadtime Insertion, Center Alignment MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 434: Top/Bottom Correction
See Figure 12- 54. On AC induction motors running open-loop, the distortion typically manifests itself as poor low-speed performance, such as torque ripple and rough operation. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 435 The direction of PWM counter if ICC bits in the PMFICCTL register are set to ones To correct deadtime distortion, software can decrease or increase the value in the appropriate PMFVAL register. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 436 Table 12-42. Top/Bottom Manual Correction Logic state Output Control IPOLA PMFVAL0 controls PWM0/PWM1 pair PMFVAL1 controls PWM0/PWM1 pair IPOLB PMFVAL2 controls PWM2/PWM3 pair PMFVAL3 controls PWM2/PWM3 pair IPOLC PMFVAL4 controls PWM4/PWM5 pair PMFVAL5 controls PWM4/PWM5 pair MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 437 However, under low-current, the output voltage of the complementary circuit during deadtime is somewhere between the high and low levels. The current cannot free-wheel through the opposition anti- body diode, regardless of polarity, giving additional distortion when the current crosses zero. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 438 Deadtime does not exist at the 100 percent and zero percent duty cycle boundaries. Therefore, the second automatic mode must be used for correction, ISENS = 11, where current status is sampled at the half cycle MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 439 PWM pairs when configured for current status correction. DESIRED LOAD VOLTAGE TOP PWM BOTTOM PWM LOAD VOLTAGE Figure 12-60. Correction with Positive Current MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 440: Asymmetric Pwm Output
PWM period. ICCx bits take effect at the end of each PWM cycle regardless of the state of the related LDOKx bit or global load OK. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 441: Variable Edge Placement Pwm Output
In contrast to asymmetric PWM output mode, the PWM phase shift can pass the PWM cycle boundary. CINV0 PECA=1 PINVA GENERATOR 0 to complement logic and CINV1 dead time insertion COMPSRC GENERATOR 1 Figure 12-63. Logic AND Function with Signal Inversions MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 442: Double Switching Pwm Output
(Figure 12-65, Figure 12-66). By setting the non-inverted value register greater or equal to the PWM modulus the output function can be switched to single pulse generation on PWM reload cycle basis. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 443 Figure 12-65. Double-Switching PWM Output VAL0<VAL1 (Center-Aligned) EDGEA=0 PECA=1 Up/Down Counter Modulus = 9 PMFVAL0 = 6; CINV0 =1 PMFVAL1 = 3; CINV1 =0 PWM0 (PINV=0) PWM0 (PINV=1) 100% Figure 12-66. Double-Switching PWM Output VAL0>VAL1 (Center-Aligned) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 444: Output Polarity
NOTE During software output control, TOPNEG and BOTNEG still control output polarity. It will take up to 3 core clock cycles to see the effect of output control on the PWM outputs. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 445 MODULUS = 4 PWM VALUE = 2 DEADTIME = 2 PWM0 PWM1 PWM0 WITH DEADTIME PWM1 WITH DEADTIME OUTCTL0 OUT0 OUT1 PWM0 PWM1 Figure 12-68. Setting OUT0 with OUTCTL Set in Complementary Mode MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 446 MODULUS = 4 PWM VALUE = 2 DEADTIME = 2 PWM0 PWM1 PWM0 WITH DEADTIME PWM1 WITH DEADTIME OUTCTL0 OUT0 OUT1 PWM0 PWM1 Figure 12-70. Setting OUTCTL with OUT0 Set in Complementary Mode MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 447: Pwm Generator Loading
PWM reload event. See Figure 12-72. bus clock LDOK write LDOK bit PWM reload bus clock LDOK write LDOK bit PWM reload Figure 12-71. Setting cleared LDOK bit at PWM reload event MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 448 Half cycle reloads are possible only in center-aligned mode. Enabling or disabling half-cycle reloads in edge-aligned mode will have no effect on the reload rate. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 449 HALF = 0, LDFQ[3:0] = 0000 = RELOAD EVERY CYCLE UP/DOWN COUNTERER LDOK = 1 MODULUS = 3 PWM VALUE = 1 PWMRF = 1 Figure 12-76. Full-Cycle Center-Aligned PWM Value Loading MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 450 Figure 12-78. Half-Cycle Center-Aligned PWM Value Loading HALF = 1, LDFQ[3:0] = 0000 = RELOAD EVERY HALF-CYCLE UP/DOWN COUNTERER LDOK = 1 MODULUS = 2 PWM VALUE = 1 PWMRF = 1 Figure 12-79. Half-Cycle Center-Aligned Modulus Loading MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 451 (PMFROIFx). If the PWM reload overrun interrupt enable bit PMFROIEx is set, the PMFROIFx flag generates a CPU interrupt request allowing software to handle the error condition. WRITE 1 TO PMFROIF RESET PMFROIF CPU INTERRUPT REQUEST PMFROIE PWM RELOAD Figure 12-82. PMFROIF Reload Overrun Interrupt Request MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 452: Fault Protection
1. The active input level may be defined or programmable at SoC level. The default for internally connected resources is active- high. For availability and configurability of fault inputs on pins refer to the device overview section. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 453 — The filter detects a logic zero on the fault input at the start of the next PWM half cycle boundary. See Figure 12-86. FAULT0 OR FAULT2 PWMS ENABLED PWMS ENABLED PWMS DISABLED FIFm CLEARED Figure 12-84. Manual Fault Recovery (Faults 0 and 2) — QSMP = 00 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 454: Resets
The gated system core clock is the clock source for all PWM generators. The system clock is used as a clock source for any other logic in this module. The system bus clock is used as clock for specific control registers and flags (LDOKx, PWMRFx, PMFOUTB). MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 455: Interrupts
The PWM generator uses the last values loaded if PWMEN is cleared and then set while LDOK equals zero. Initializing the deadtime register, after setting PWMEN or OUTCTLn, can cause an improper deadtime insertion. However, the deadtime can never be shorter than the specified value. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 456: Bldc 6-Step Commutation
Make sure to set the write protection bit WP in PMFCFG0 after configuring and prior to enabling PWM outputs and fault inputs. 12.8.2 BLDC 6-Step Commutation 12.8.2.1 Unipolar Switching Mode Unipolar switching mode uses registers PMFOUTC and PMFOUTB to perform commutation. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 457 // Invert B The commutation sequence is: PMFCFG2[MSK5:MSK0] = 0x03; // Branch C<->B, mask A // 60° PMFCFG3[PINVC,PINVB,PINVA] = 0x2; // Invert B PMFCFG2[MSK5:MSK0] = 0x0c; // Branch C<->A, mask B // 120° MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 458 PWM0 PWMgen Masked PWMgen Masked PWMgen PWM1 PWMgen Masked PWMgen Masked PWMgen PWM2 PWMgen Masked PWMgen Masked PWM3 PWMgen Masked PWMgen Masked PWM4 Masked PWMgen Masked PWMgen PWM5 Masked PWMgen Masked PWMgen MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 459: Introduction
Software generated reload event and Trigger event generation for debugging 13.1.2 Modes of Operation The PTU module behaves as follows in the system power modes: 1. Run mode All PTU features are available. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 460: Block Diagram
External Signal Description This section lists the name and description of all external ports. 13.2.1 PTUT0 — PTU Trigger 0 If enabled (PTUT0PE is set) this pin shows the internal trigger_0 event. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 461: Pture — Ptue Reload Event
0x0003 TG0AEIE TG0REIE TG0TEIE TG0DIE PTUIEL 0x0004 PTUDEEF PTUROIF PTUIFH 0x0005 TG0AEIF TG0REIF TG0TEIF TG0DIF PTUIFL 0x0006 TG0LIST TG0LIST 0x0007 TG0TNUM[4:0] TG0TNUM 0x0008 TG0TV[15:8] TG0TVH = Unimplemented Figure 13-2. PTU Register Summary MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 462: Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. Unused bits read back zero. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 463 At the next reload event this bit is cleared by control logic. Write 0 is only possible if TG0EN is cleared. The PTULDOK can be used by other module as global load OK (glb_ldok). MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 464 Trigger Generator 0 Reload Error Interrupt Enable — Enables trigger generator reload error interrupt. TG0REIE 0 No interrupt will be requested whenever TG0REIF is set 1 Interrupt will be requested whenever TG0REIF is set MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 465 Trigger Generator 0 Done Interrupt Enable — Enables trigger generator done interrupt. TG0DIE 0 No interrupt will be requested whenever TG0DIF is set 1 Interrupt will be requested whenever TG0DIF is set MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 466 13.3.2.6 Module Base + 0x0005 Access: User read/write TG0AEIF TG0REIF TG0EIF TG0DIF Reset = Unimplemented Figure 13-8. PTU Interrupt Flag Register Low (PTUIFL) 1. Read: Anytime Write: Anytime, write 1 to clear MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 467 Trigger Generator 0 Done Interrupt Flag —This bit is set if the trigger generator receives the end of list symbol TG0DIF or the maximum number of generated trigger events was reached. 0 Trigger generator 0 is running 1 Trigger generator 0 is done MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 468 Trigger Generator 0 Trigger Number — This register shows the number of generated triggers since the last TG0TNUM[4:0] reload event. After the generation of 32 triggers this register shows zero. The next reload event clears this register. See also Figure 13-17. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 469 (EOL) symbol then this value is visible inside this register. If the last generated trigger was trigger number 32 then the last used trigger value is visible inside this register. See also Figure 13-17. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 470 PTUCNT[15:0] PTU Time Base Counter value — This register contains the current status of the internal time base counter. If both TG are done with the execution of the trigger list then the counter also stops. The counter is restarted by the next reload event. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 471 PTU Pointer — This register cannot be modified if TG0EN bit is set. This register defines the start address of [23:0] the used list area inside the global memory map. For more information see Section 13.4.2, “Memory based trigger event list”. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 472 Trigger Generator 0 List 1 Index Register — This register cannot be modified after the TG0EN bit is set. This TG0L1IDX register defines offset of the start point for the trigger event list 1 used by trigger generator 0. For more [6:0] information see Section 13.4.2, “Memory based trigger event list”. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 473: Functional Description
TG0 wait for the next match. So up to 32 trigger events per control cycle can be generated. If the trigger value is 0x0000 or 32 trigger events have been MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 474: Memory Based Trigger Event List
The trigger values inside the trigger list are 16 bit values. Each 16 bit value defines the delay between the reload event and the trigger event in bus clock cycles. A delay value of 0x0000 will be interpreted as End MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 475: Reload Mechanism
The time window to update the trigger list starts at the trigger generator done interrupt flag (TG0DIF) and ends with the next reload event. Even if only one MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 476: Async Reload Event
If the trigger generator reads trigger values from the memory which contains double bit ECC errors then the PTUDEEF is set. These read data are ignored and the execution of the trigger generator is stopped until MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 477 If the trigger value loaded from the memory contains double bit ECC errors (PTUDEEF flag is set) then the data are ignored and the trigger generator timing error flag (TG0TEIF) is not set. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 478: Debugging
To generate a reload event or trigger event independent from the PWM status the debug register bits PTUFRE or TG0FTE can be used. A write one to this bits will generate the associated event. This behavior is not available during stop or freeze mode. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 479: Introduction
Chapter 14 Serial Communication Interface (S12SCIV6) Table 14-1. Revision History Version Revision Effective Author Description of Changes Number Date Date 05.03 12/25/2008 remove redundancy comments in Figure1-2 fix typo, SCIBDL reset value be 0x04, not 0x00 05.04 08/05/2009 fix typo, Table 14-4,SCICR1 Even parity should be PT=0 05.05...
Page 480: Features
— Framing error — Parity error — Receive wakeup on active edge — Transmit collision detect supporting LIN — Break Detect supporting LIN • Receiver framing error detection • Hardware parity checking MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 481: Modes Of Operation
Baud Rate Generator Infrared Data Out TXD Transmit Shift Register Encoder SCI Data Register Figure 14-1. SCI Block Diagram 14.2 External Signal Description The SCI module has a total of two external pins. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 482: Txd — Transmit Pin
SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 SCIBDL 0x0002 LOOPS SCISWAI RSRC WAKE SCICR1 0x0000 RXEDGIF BERRV BERRIF BKDIF SCIASR1 = Unimplemented or Reserved Figure 14-2. SCI Register Summary (Sheet 1 of 2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 483 Figure 14-3. SCI Baud Rate Register (SCIBDH) Module Base + 0x0001 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 Reset Figure 14-4. SCI Baud Rate Register (SCIBDL) Read: Anytime, if AMAP = 0. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 484 Figure 14-5. SCI Control Register 1 (SCICR1) Read: Anytime, if AMAP = 0. Write: Anytime, if AMAP = 0. NOTE This register is only visible in the memory map if AMAP = 0 (reset condition). MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 485 0 Even parity 1 Odd parity Table 14-5. Loop Functions LOOPS RSRC Function Normal operation Loop mode with transmitter output internally connected to receiver input Single-wire mode with TXD pin connected to receiver input MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 486 Module Base + 0x0001 RXEDGIE BERRIE BKDIE Reset = Unimplemented or Reserved Figure 14-7. SCI Alternative Control Register 1 (SCIACR1) Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 487 Bit Error Mode — Those two bits determines the functionality of the bit error detect feature. See Table 14-10. BERRM[1:0] Break Detect Feature Enable — BKDFE enables the break detect circuitry. BKDFE 0 Break detect circuit disabled 1 Break detect circuit enabled MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 488 Receiver Full Interrupt Enable Bit — RIE enables the receive data register full flag, RDRF, or the overrun flag, OR, to generate interrupt requests. 0 RDRF and OR interrupt requests disabled 1 RDRF and OR interrupt requests enabled MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 489 Module Base + 0x0004 TDRE RDRF IDLE Reset = Unimplemented or Reserved Figure 14-10. SCI Status Register 1 (SCISR1) Read: Anytime Write: Has no meaning or effect MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 490 RDRF flag but does not get set in the case of an overrun. Clear NF by reading SCI status register 1(SCISR1), and then reading SCI data register low (SCIDRL). 0 No noise 1 Noise MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 491 0 Normal polarity 1 Inverted polarity MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 492 Module Base + 0x0007 Reset Figure 14-13. SCI Data Registers (SCIDRL) Read: Anytime; reading accesses SCI receive data register Write: Anytime; writing accesses SCI transmit data register; writing to R8 has no effect MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 493: Functional Description
CPU and remote devices, including other CPUs. The SCI transmitter and receiver operate independently, although they use the same baud rate generator. The CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 494: Infrared Interface Submodule
The infrared submodule consists of two major blocks: the transmit encoder and the receive decoder. The SCI transmits serial bits of data which are encoded by the infrared submodule to transmit a narrow pulse MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 495: Lin Support
The SCI uses the standard NRZ mark/space data format. When Infrared is enabled, the SCI uses RZI data format where zeroes are represented by light pulses and ones remain low. See Figure 14-15 below. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 496: Baud Rate Generation
A 16-bit modulus counter in the two baud rate generator derives the baud rate for both the receiver and the transmitter. The value from 0 to 65535 written to the SBR15:SBR0 bits determines the baud rate. The value MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 497 76,804.9 4800.3 4,800 .006 10417 38,398.8 2399.9 2,400 .003 20833 19,200.3 1200.02 1,200 41667 9599.9 600.0 65535 6103.6 381.5 1. 16x faster then baud rate 2. divide 1/16 form transmit baud generator MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 498: Transmitter
TXD pin, after it has prefaced them with a start bit and appended them with a stop bit. The SCI data registers (SCIDRH and SCIDRL) are the write-only buffers between the internal data bus and the transmit shift register. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 499 If the transmit interrupt enable bit, TIE, in SCI control register 2 (SCICR2) is also set, the TDRE flag generates a transmitter interrupt request. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 500 Does not clear the SCI data registers (SCIDRH/L) • May set noise flag NF, or receiver active flag RAF. 1. A Break character in this context are either 10 or 11 consecutive zero received bits MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 501 TDRE flag is set and immediately before writing the next byte to the SCI data register. If the TE bit is clear and the transmission is complete, the SCI is not the master of the TXD pin MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 502 If the bit error detect feature is disabled, the bit error interrupt flag is cleared. NOTE The RXPOL and TXPOL bit should be set the same when transmission collision detect feature is enabled, otherwise the bit error interrupt flag may be set incorrectly. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 503: Receiver
After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCISR1) becomes set, MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 504 Table 14-18. Start Bit Verification RT3, RT5, and RT7 Samples Start Bit Verification Noise Flag If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 505 The RT clock is reset and the start bit search begins again. The noise flag is not set because the noise occurred before the start bit was found. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 506 RT5 is high. The RT5 sample sets the noise flag. Although this is a worst-case misalignment of perceived bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 507 Depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may set the framing error flag. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 508 A framing error will occur if the receiver clock is misaligned in such a way that the majority of the RT8, RT9, and RT10 stop bit samples are a logic zero. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 509 Fast Data Tolerance Figure 14-29 shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 510 SCIDRH/L registers, but it will not set the RDRF flag. The transmitting device can address messages to selected receivers by including addressing information in the initial frame or frames of each message. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 511: Single-Wire Operation
Normally, the SCI uses two pins for transmitting and receiving. In single-wire operation, the RXD pin is disconnected from the SCI. The SCI uses the TXD pin for both receiving and transmitting. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 512: Loop Operation
NOTE In loop operation data from the transmitter is not recognized by the receiver if RXPOL and TXPOL are not the same. 14.5 Initialization/Application Information 14.5.1 Reset Initialization Section 14.3.2, “Register Descriptions”. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 513: Modes Of Operation
Active high level. Indicates that receiver input has become idle. RXEDGIF SCIASR1[7] RXEDGIE Active high level. Indicates that an active edge (falling for RXPOL = 0, rising for RXPOL = 1) was detected. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 514 The newly acquired data in the shift register will be lost in this case, but the data already in the SCI data registers is not affected. The OR interrupt is cleared by reading the SCI status register one (SCISR1) and then reading SCI data register low (SCIDRL). MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 515: Recovery From Wait Mode
The SCI interrupt request can be used to bring the CPU out of wait mode. 14.5.5 Recovery from Stop Mode An active edge on the receive input can be used to bring the CPU out of stop mode. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 516 Chapter 14 Serial Communication Interface (S12SCIV6) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 517: Introduction
Chapter 15 Serial Peripheral Interface (S12SPIV5) Table 15-1. Revision History Revision Sections Revision Date Description of Changes Number Affected V05.00 24 Mar 2005 15.3.2/15-521 - Added 16-bit transfer width feature. 15.1 Introduction The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices.
Page 518: Block Diagram
Figure 15-1 gives an overview on the SPI architecture. The main parts of the SPI are status, control and data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 519: External Signal Description
MOSI — Master Out/Slave In Pin This pin is used to transmit data out of the SPI module when it is configured as a master and receive data when it is configured as slave. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 520: Miso — Master In/Slave Out Pin
BIDIROE SPISWAI SPC0 SPICR2 0x0002 SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 SPIBR 0x0003 SPIF SPTEF MODF SPISR 0x0004 SPIDRH 0x0005 SPIDRL 0x0006 Reserved = Unimplemented or Reserved Figure 15-2. SPI Register Summary MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 521: Register Descriptions
SPI modules must have identical CPOL values. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 Active-high clocks selected. In idle state SCK is low. 1 Active-low clocks selected. In idle state SCK is high. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 522 Module Base +0x0001 XFRW MODFEN BIDIROE SPISWAI SPC0 Reset = Unimplemented or Reserved Figure 15-4. SPI Control Register 2 (SPICR2) Read: Anytime Write: Anytime; writes to the reserved bits have no effect MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 523 Master In Master Out Bidirectional MISO not used by SPI Master In Master I/O Slave Mode of Operation Normal Slave Out Slave In Bidirectional Slave In MOSI not used by SPI Slave I/O MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 524 Baud Rate SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate Divisor 12.5 Mbit/s 6.25 Mbit/s 3.125 Mbit/s 1.5625 Mbit/s 781.25 kbit/s 390.63 kbit/s 195.31 kbit/s 97.66 kbit/s 6.25 Mbit/s 3.125 Mbit/s 1.5625 Mbit/s MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 525 39.06 kbit/s 1280 19.53 kbit/s 2.08333 Mbit/s 1.04167 Mbit/s 520.83 kbit/s 260.42 kbit/s 130.21 kbit/s 65.10 kbit/s 32.55 kbit/s 1536 16.28 kbit/s 1.78571 Mbit/s 892.86 kbit/s 446.43 kbit/s 223.21 kbit/s 111.61 kbit/s MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 526 (SPICR2)”. The flag is cleared automatically by a read of the SPI status register (with MODF set) followed by a write to the SPI control register 1. 0 Mode fault has not occurred. 1 Mode fault has occurred. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 527 2. Data in SPIDRH is undefined in this case. 3. SPIDRH can be written repeatedly without any effect on SPTEF. SPTEF Flag is cleared only by writing to SPIDRL after reading SPISR with SPTEF == 1. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 528 If SPIF is set and valid data is in the receive shift register, and SPIF is serviced after the start of a third transmission, the data in the receive shift register has become invalid and is not transferred into the SPIDR (see Figure 15-10). MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 529: Functional Description
The SPI system is enabled by setting the SPI enable (SPE) bit in SPI control register 1. While SPE is set, the four associated SPI port pins are dedicated to the SPI function as: • Slave select (SS) • Serial clock (SCK) • Master out/slave in (MOSI) • Master in/slave out (MISO) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 530: Master Mode
If the SS input becomes low this indicates a mode fault error where another master tries to 1. n depends on the selected transfer width, please refer to Section 15.3.2.2, “SPI Control Register 2 (SPICR2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 531: Slave Mode
SPI data in a slave mode. For these simpler devices, there is no serial data out pin. NOTE When peripherals with duplex capability are used, take care not to simultaneously enable two receivers whose serial outputs drive the same system slave’s serial data output line. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 532: Transmission Formats
Using two bits in the SPI control register 1, software selects one of four combinations of serial clock phase and polarity. 1. n depends on the selected transfer width, please refer to Section 15.3.2.2, “SPI Control Register 2 (SPICR2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 533 SPI. 1. n depends on the selected transfer width, please refer to Section 15.3.2.2, “SPI Control Register 2 (SPICR2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 534 , and t are guaranteed for the master mode and required for the slave mode. Figure 15-12. SPI Clock Format 0 (CPHA = 0), with 8-bit Transfer Width selected (XFRW = 0) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 535 A half SCK cycle later, the second edge appears on the SCK pin. This is the latching edge for both the master and slave. 1. n depends on the selected transfer width, please refer to Section 15.3.2.2, “SPI Control Register 2 (SPICR2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 536 = Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers Figure 15-14. SPI Clock Format 1 (CPHA = 1), with 8-Bit Transfer Width selected (XFRW = 0) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 537: Spi Baud Rate Generation
The SPI clock rate is determined by the product of the value in the baud rate preselection bits (SPPR2–SPPR0) and the value in the baud rate selection bits (SPR2–SPR0). The module clock divisor equation is shown in Equation 15-3. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 538: Special Features
The MOSI pin becomes the serial data I/O (MOMI) pin for the master mode, and the MISO pin becomes serial data I/O (SISO) pin for the slave mode. The MISO pin in master mode and MOSI pin in slave mode are not used by the SPI. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 539: Error Conditions
In the special case where the SPI is in master mode and MODFEN bit is cleared, the SS pin is not used by the SPI. In this special case, the mode fault error function is inhibited and MODF remains cleared. In case MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 540: Low Power Mode Options
SPIDR to the master, it will continue to send the same byte. Else if the slave is currently sending the last received byte from the master, it will continue to send each previous master byte). MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 541 The MODF interrupt is reflected in the status register MODF flag. Clearing the flag will also clear the interrupt. This interrupt will stay active while the MODF flag is set. MODF has an automatic clearing process which is described in Section 15.3.2.4, “SPI Status Register (SPISR)”. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 542 SPTEF occurs when the SPI data register is ready to accept new data. After SPTEF is set, it does not clear until it is serviced. SPTEF has an automatic clearing process, which is described in Section 15.3.2.4, “SPI Status Register (SPISR)”. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 543: Introduction
Chapter 16 High-Side Driver Module - HSDRV2C (HSDRV2CV3) Table 16-1. Revision History Table Rev. No. Date Sections Substantial Change(s); (Item No.) (Submitted By) Affected V1.00 10 December - Initial 2010 V2.00 07 Sep - Added description and register bits for over-current masking feature 2012 V2.02 05 August 2013...
Page 544: Modes Of Operation
HSDRV2C module. The module consists of a control and an output stage. The high-side driver gate control can be routed. See PIM chapter for routing options. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 545: External Signal Description
Power supply for the high-side driver. This pin must be connected to the main power supply with the appropriate reverse battery protection network. 16.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the HSDRV2C module. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 546: Module Memory Map
HSE1 HSE0 HSCR 0x0002 HSSLCU1 HSSLCU0 HSSLEN1 HSSLEN0 HSSLR 0x0003 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x0004 Reserved HSOL1 HSOL0 0x0005 HSSR 0x0006 HSOCIE HSIE 0x0007 HSOCIF1 HSOCIF0 HSIF MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 547: Register Definition
HS_settling 16.3.4 HSDRV2C Configuration Register (HSCR) Module Base + 0x0001 Access: User read/write HSOCME1 HSOCME0 HSOLE1 HSOLE0 HSE1 HSE0 Reset = Unimplemented Figure 16-3. HSDRV2C Configuration Register (HSCR) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 548 1 High-side driver is enabled Note: After enabling the high-side driver (HSCR[HSEx]=1), a settling time t is required before the high-side HS_settling driver is allowed to be turned on (e.g. by writing to the HSDR). MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 549: Hsdrv2C Slew Rate Control Register (Hsslr)
The voltage slew rate is limited for ~8 us when the associated driver is switched on to reduce the emission if the high-side driver is used as an off-board driver. These bits are only writable if the associated high-side driver is disabled (HSCR[HSEx]=0) 0 Slew rate control disabled 1 Slew rate contol enabled MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 550: Reserved Register
Table 16-7. Reserved Register Field Descriptions Field Description These reserved bits are used for test purposes. Writing to these bits can alter the module functionality. Reserved MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 551: Hsdrv2C Status Register (Hssr)
Write: Anytime Table 16-9. HSDRV Interrupt Enable Register (HSIE) Field Descriptions Field Description HSDRV2C Over-Current Interrupt Enable HSOCIE 0 Interrupt request is disabled 1Interrupt is requested whenever a HSIF[HSOCIFx] flag is set MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 552: Hsdrv2C Interrupt Flag Register (Hsif)
If the driving pin HS[x] stays at a HVOLDC voltage above an internal threshold then an open load will be detected for the associated high-side driver. The open-load condition is flagged in the HSDRV Status Register (HSSR). MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 553: Over-Current Shutdown
HSDRV2C Over-Current Interrupt (HSOCI) HSOCIE = 1 If an over-current is detected the related interrupt flag HSOCIFx asserts. Depending on the setting of the HSDRV2C Error Interrupt Enable (HSOCIE) bit an interrupt is requested. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 554 Chapter 16 High-Side Driver Module - HSDRV2C (HSDRV2CV3) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 555: Introduction
Chapter 17 LIN Physical Layer (S12LINPHYV2) Table 17-1. Revision History Table Rev. No. Date Sections Substantial Change(s) (Item No.) (Submitted By) Affected 10 Dec 2010 V01.00 - Initial Version 25 June 2012 V02.00 - Added LIN TxD-dominant timeout feature 11 Jan 2013 -Added application note to help the ISR development for the Interrupts V02.06 (timeout and overcurrent)
Page 556: Modes Of Operation
LIN Physical Layer sends a wake-up pulse to the SCI, which requests a wake-up interrupt. (This feature is only available if the LIN Physical Layer is routed to the SCI). MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 557: Block Diagram
The external 220 pF capacitance between LIN and LGND is strongly recommended for correct operation. 17.2 External Signal Description This section lists and describes the signals that connect off chip as well as internal supply nodes and special signals. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 558: Lin — Lin Bus Pin
Detailed descriptions of the registers and bits are given in the subsections that follow. NOTE Register Address = Module Base Address + Address Offset, where the Module Base Address is defined at the MCU level and the Address Offset is defined at the module level. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 559: Register Descriptions
Reserved LPDT 0x0005 LPSR 0x0006 LPDTIE LPOCIE LPIE 0x0007 LPDTIF LPOCIF LPIF Figure 17-2. Register Summary 17.3.2 Register Descriptions This section describes all the LIN Physical Layer registers and their individual bits. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 560 Receive Only Mode bit — This bit controls RXONLY mode. RXONLY 0 The LIN Physical Layer is not in receive only mode. 1 The LIN Physical Layer is in receive only mode. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 561 LIN Slew Rate Mode Register (LPSLRM) Module Base + Address 0x0003 Access: User read/write LPDTDIS LPSLR1 LPSLR0 Reset = Unimplemented Figure 17-6. LIN Slew Rate Mode Register (LPSLRM) 1. Read: Anytime Write: Only in shutdown mode (LPE=0) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 562 Table 17-6. Reserved Register Field Description Field Description These reserved bits are used for test purposes. Writing to these bits can alter the module functionality. Reserved MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 563 1 LPTxD is still dominant after a TxD-dominant timeout. 17.3.2.7 LIN Interrupt Enable Register (LPIE) Module Base + Address 0x0006 Access: User read/write LPDTIE LPOCIE Reset = Unimplemented Figure 17-9. LIN Interrupt Enable Register (LPIE) 1. Read: Anytime Write: Anytime MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 564 If the overcurrent is still present or LPTxD is dominant after clearing the flag, the transmitter stays disabled and this flag is set again (see17.4.4.1 Overcurrent Interrupt). If interrupt requests are enabled (LPOCIE= 1), LPOCIF causes an interrupt request. 0 No overcurrent event has occurred. 1 Overcurrent event has occurred. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 565: Functional Description
A stronger external pullup resistor might be necessary to sustain communication speeds up to 250 kbit/s. The LIN signal (and therefore the receive LPRxD signal) might not be symmetrical for high baud rates with high loads on the bus. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 566: Modes
If LPWUE is not set, no wake up feature is available and the standby mode has the same electrical properties as the shutdown mode. This allows a low-power consumption of the device in stop mode if the wake-up feature is not needed. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 567 SCI interrupt, then the SCI interrupt will execute first). It is up to the software to decide what to do in this case because the LIN Physical Layer can not guarantee it was a valid wake-up pulse. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 568 # $ " ! " ! % % ! " ! " ! # $ " ! Figure 17-11. LIN Physical Layer Mode Transitions MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 569: Interrupts
2 IRC periods (2 us) + 3 bus periods If the bit LPOCIE is set in the LPIE register, an interrupt is requested. Figure 17-12 shows the different scenarios for overcurrent interrupt handling. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 570 To re-enable the transmitter then, the LPDTIF flag must be cleared (by writing a 1). NOTE Please make sure that LPDTIF=1 before trying to clear it. It is not allowed to try to clear LPDTIF if LPDTIF=0 already. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 571 ! "! ! ! # ! "! ! ! "! Figure 17-13. TxD-dominant timeout interrupt handling MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 572: Application Information
— If the receiver must remain enabled, set the LIN Physical Layer into receive only mode instead. 2. Do all required configurations (SCI, etc.) to re-enable the transmission. 3. Wait for a transmit bit (this is needed to successfully re-enable the transmitter). 4. Clear the error flag. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 573 7. Wait for a minimum of a transmit bit before beginning transmission again. If there is a problem re-enabling the transmitter, then the error flag will be set again during step 3 and the ISR will be called again. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 574 Chapter 17 LIN Physical Layer (S12LINPHYV2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 575: Introduction
Chapter 18 Gate Drive Unit (GDU2PHV2) Table 18-1. Revision History Table Version Revision Date Description of Changes Number V02.00 29-July-2016 Added Note to Figure 18-1 18.2.5/18-578 on VLS pin. V02.01 16-Sep-2016 Global renaming of HD pin to GHD Corrected pin names in Table 18-9.
Page 576 GDU charge pump clock is not running. This means device can not be put in stop mode if FETs needs to be in specific state to protect the system. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 577: Block Diagram
1. On some devices VLS[1] and VLS[0] are connected together internally and routed to a single VLS pin. The device overview information specifies if a single VLS pin or VLS[1:0] are featured. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 578: External Signal Description
GLG[1:0] — Low-Side Gate Pins These pins are the gate drives for the low-side power FETs. The drivers provide a high current with low impedance to turn on and off the the low-side power FETs. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 579: Memory Map And Register Definition
A 4.7uF or 10uF capacitor should be connected to this pin for stability of the the voltage regulator output. 18.3 Memory Map and Register Definition This section provides the detailed information of all registers for the GDU2PH module. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 580: Register Summary
0x0006 GSUF GHHDF GLVLSF GOCIF0 GHHDIF GLVLSIF GDUF 0x0007 Reserved 0x0008 Reserved 0x0009 GPHMX[1:0] GDUPHMUX 0x000A GCSO0[2:0] GDUCSO 0x000B R GDSFHS GDSFLS GDSLHS[2:0] GDSLLS[2:0] GDUDSLVL = Unimplemented Figure 18-2. GDU Register Summary MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 581: Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. Unused bits read back zero. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 582 FET pre-drivers. In order to switch on and off the FET pre-drivers the PMF module has to be used to mask and un-mask the PWM channels. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 583 GBKTIM1 & GBKTIM2 must not change. If a different blanking time is required, the PWM channel has to be turned off before new values to GBKTIM1 & GBKTIM2 are written. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 584 GDU Desaturation Error Flag Register (GDUDSE) 18.3.2.4 Module Base + 0x0003 Access: User read/write GDHSIF[1:0] GDLSIF[1:0] Reset = Unimplemented Figure 18-6. GDU2PH Desaturation Error Flag Register (GDUDSE) 1. Read: Anytime Write: Anytime, write 1 to clear MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 585 GLS[1:0] occurs. If the GDSEIE bit is set an interrupt is requested. Writing a logic “1” to the bit field clears the flag. 0 No desaturation error on low-side driver 1 Desaturation error on low-side driver MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 586 1 Voltage on pin VLS_OUT is less than V LVLSA GDU Slew Rate Control Register (GDUSRC) 18.3.2.6 Module Base + 0x0005 Access: User read/write GSRCHS[2:0] GSRCLS[2:0] Reset = Unimplemented Figure 18-8. GDU Slew Rate Control Register (GDUSRC) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 587 GDU Slew Rate Control Bits Low-Side FET Pre-Drivers — These bits control the slew rate on the LG[2:0] GSRCLS[2:0] pins (see FET Pre-Driver Details). These bits cannot be modified after GWP bit is set. 000 : slowest 111 : fastest MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 588 GDU Low VLS Supply Interrupt Flag— The interrupt flag is set by hardware if GLVLSF is set or GLVLSS is GLVLSIF cleared. If the GLVLSIE bit is set an interrupt is requested.Writing a logic “1” to the bit field clears the flag. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 589 / 12 connected to ADC channel 01 Pin GHS0 selected , V / 6 connected to ADC channel 10 Pin GHS1 selected , V / 6 connected to ADC channel 11 Reserved. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 590 18.3.2.10 GDU Desaturation Level Register (GDUDSLVL) Module Base + 0x000B Access: User read/write GDSFHS GDSLHS[2:0] GDSFLS GDSLLS[2:0] Reset = Unimplemented Figure 18-12. GDU Desaturation Level Register (GDUDSLVL) 1. Read: Anytime Write: Only if GWP=0 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 591 These bits cannot be modified after GWP bit is set. See Section 18.4.5, “Desaturation Error 000 V = 0.35V (typical value) desatls 001 to 110 see device electrical specification 111 V = 1.40V (typical value) desatls MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 592 The GCPCD bits must be set to the required value before GCPE bit is set. If a different charge pump clock frequency is required GCPE has to be cleared before new values to GCPCD bits are written. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 593 / 96 0110 / 100 0111 / 128 1000 / 192 1001 / 200 1010 / 256 1011 / 384 1100 / 400 1101 / 512 1110 / 768 1111 / 800 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 594 GDU Control Register 1 (GDUCTR1) 18.3.2.14 Module Base + 0x0010 Access: User read/write GBSWOFF[1:0] TDEL Reset = Unimplemented Figure 18-16. GDU Control Register 1 (GDUCTR1) 1. Read: Anytime Write: Only if GWP=0 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 595: Functional Description
18-17. The register bits GSRCLS[2:0] in the GDUSRC Register (see Figure 18-8) control the slew rate of the low-side FET pre-drivers in order to control fast voltage changes dv/dt (see also Section 18.5.1, “FET Pre-Driver Details). MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 596: High-Side Fet Pre-Driver
V ~ 0V and V ~ 0V so that the external FETs are turned off. NOTE The PWM channel outputs for high-side and low-side drivers are delayed by two core clock cycles. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 597 Figure 18-17. FET Pre-Driver Circuit and Voltage Regulator NOTE Optional charge pump input RC filter can be used to avoid over pumping effect when voltage spikes are present on the high-side drains. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 598: Charge Pump
: Blanking Time (see GDUCTR register) BLANK GCPE delon predrivers on deloff BLANK charge pump connect HGON HGOFF During this time desaturation error flags can be set and charge pump is connected to VBSx MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 599: Desaturation Error
The low-side and high-side desaturation interrupt flags GDHSIF and GDLSIF are cleared by writing a one to the associated flag. After the flag is cleared the associated low-side or high-side FET pre-driver is enabled again and is driven by the source selected in the PMF module. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 600: Phase Comparators
GPHS[1:0] is cleared. If a desaturation error is detected the state of the phase status bit GPHS[1:0] are copied to the GDUPHL register. The phase flags get unlocked when the associated desaturation interrupt flag is cleared. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 601: Fault Protection Features
[0] | [0]) | ( [0] & GDLSIF GDHSIF GOCIF GOCA Fault[1] [1] | [1]) | ( [0] & GDLSIF GDHSIF GOCIF GOCA Fault[2] GLVLSF Fault[3] 0 & ~ GHHDF GOCIF GOCA MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 602 Table 18-20. Fault Protection Features Summary Prior GDHSIF GDLSIF Condition GSUF GHHDF GOCIF0 GLVLSF [1:0] [1:0] normal operation,no error condition, FET pre-driver driven by PMF module startup condition after reset deassert, no error condition overvoltage on GHD pin GOVA=0 overcurrent condition comparator 0 GOCA0=0 undervoltage condition on VLS_OUT pin overcurrent condition comparator 0...
Page 603 Figure 18-21. Short to Supply Detection GLGx BLANK GHGx GHSx shorted to supply 0.5 V GHSx correct voltage on GHSx fault Phase Status correct Desat. Error...
Page 604 Chapter 18 Gate Drive Unit (GDU2PHV2) Figure 18-22. Short to Ground Detection GHGx BLANK GLGx correct voltage on GHSx GHSx 0.5 V GHSx shorted to ground correct Phase Status fault Desat. Error MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 605: Current Sense Amplifier And Overcurrent Comparator
Section 18.3.2.8, “GDU Phase Mux Register (GDUPHMUX) voltage on pin GHD divide by 5 is routed to an ADC channel. See device specific information for ADC channel number. This feature is only available if GFDE is set. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 606: Interrupts
GDU low voltage condition on pin VLS GLVLSIE = 1 detection and overcurrent (GLVLSIF) detection interrupt GDU high voltage condition on pin GHD GHHDIE = 1 (GHHDIF) GDU Overcurrent Condition GOCIE0=1 (GOCIF0) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 607: Application Information
HSpul • = k I OUT1 OUT2 • ) (1+k) OUT1 OUT2 • Figure 18-24. FET Pre-Driver Concept for High-Side Driver out2 out1 gduon Driver On GSRCHS[2:0] Driver Off HSpul gduoffn gduoffp MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 608: Gdu Intrinsic Dead Time
PMF module is required and the PWM channels can change at the same time without cross conduction of the power MOSFETs. 1. Note that t and t is the turn on and turn off time for high-side and low-side gate HGON HGOFF MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 609 HGOFF_min GLG0 min turn off delay and min turn off time deloff_min HGOFF_min dead time = t delon_max deloff_max HGOFF_max GLG0 max turn off delay and max turn off time deloff_max HGOFF_max MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 610 5. Use software control of PWM output feature PMFOUTC and PMFOUTB to deassert PWM0 • 6. Store measured pulse width (t of high-side driver 0) in RAM deloff • repeat 3 to 6 for all PWM channels MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 611 Figure 18-27. Measurement of GDU t and t delon deloff PWM0 hs0_fb delon deloff PWM1 ls0_fb delon deloff gdu_delay_on_off Signal routed to TIM1 IOC1_0 for pulse width measurement...
Page 612 Chapter 18 Gate Drive Unit (GDU2PHV2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 613: Introduction
Chapter 19 Flash Module (S12ZFTMRZ) Table 19-1. Revision History Revision Revision Sections Description of Changes Number Date Affected V02.03 12 Apr 2012 19.3/19-618 Corrected many typo. Changed caution note V02.04 17 May 2012 19.3.2.6/19-630 - Removed flag DFDIE V02.05 11 Jul 2012 - Added explanation about when MGSTAT[1:0] bits are cleared, Section 19.3.2.7 - Added note about possibility of reading P-Flash and EEPROM...
Page 614: Glossary
It is possible to read from P-Flash memory while some commands are executing on EEPROM memory. It is not possible to read from EEPROM memory while a command is executing on P-Flash memory from the same block. Simultaneous P-Flash and EEPROM operations are discussed in Section 19.4.6.
Page 615: Block Diagram
Interrupt generation on Flash command completion and Flash error detection • Security mechanism to prevent unauthorized access to the Flash memory 19.1.3 Block Diagram The block diagrams of the Flash modules are shown in the following figures. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 616 Interface 16bit Command Registers Interrupt internal P-Flash Request sector 0 Error Protection sector 1 Interrupt Request final sector Security Clock Clock Divider FCLK Memory Controller EEPROM sector 0 sector 1 final sector MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 617: External Signal Description
FCLK Memory Controller EEPROM P-Flash sector 0 sector 0 sector 1 sector 1 final sector final sector HardBlock-0N (P-Flash+EEPROM) 19.2 External Signal Description The Flash module contains no signals that connect off-chip. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 618: Memory Map And Registers
Default protection settings as well as security information that allows the MCU to restrict access to the Flash module are stored in the Flash configuration field as described in Table 19-4. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 619 Section 19.3.2.2, “Flash Security Register (FSEC)” 1. 0xFF_FE08-0xFF_FE0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0xFF_FE0A - 0xFF_FE0B reserved field should be programmed to 0xFF. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 620 Flash Protected/Unprotected Higher Region 0xFF_E000 2, 4, 8, 16 KB 0xFF_F000 0xFF_F800 Flash Configuration Field P-Flash END = 0xFF_FFFF 16 bytes (0xFF_FE00 - 0xFF_FE0F) Figure 19-2. P-Flash Memory Map With Protection Alignment MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 621 Reserved 0x1F_9800 – 0x1F_BFFF 10,240 Reserved 0x1F_C000 – 0x1F_C0FF P-Flash IFR (see Table 19-5) 0x1F_C100 – 0x1F_C1FF Reserved. 0x1F_C200 – 0x1F_FFFF 15,872 Reserved. 1. See Section 19.4.4 for NVM Resources Area description. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 622: Register Descriptions
& Name FDIVLD 0x0000 FDIVLCK FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 FCLKDIV KEYEN1 KEYEN0 RNV5 RNV4 RNV3 RNV2 SEC1 SEC0 0x0001 FSEC 0x0002 CCOBIX2 CCOBIX1 CCOBIX0 FCCOBIX Figure 19-4. FTMRZ128K512 Register Summary MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 623 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 FCCOB1HI 0x000F CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 FCCOB1LO 0x0010 CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 FCCOB2HI Figure 19-4. FTMRZ128K512 Register Summary (continued) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 624 All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times but bit 7 remains unwritable. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 625 40.6 0x27 14.6 15.6 0x0E 40.6 41.6 0x28 15.6 16.6 0x0F 41.6 42.6 0x29 16.6 17.6 0x10 42.6 43.6 0x2A 17.6 18.6 0x11 43.6 44.6 0x2B 18.6 19.6 0x12 44.6 45.6 0x2C MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 626 Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 19-11. If the SEC[1:0] Flash module is unsecured using backdoor key access, the SEC bits are forced to 10. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 627 See 19.3.2.13 Flash Common Command Object Registers (FCCOB),” for more details. 19.3.2.4 Flash Protection Status Register (FPSTAT) This Flash register holds the status of the Protection Override feature. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 628 = Unimplemented or Reserved Figure 19-9. Flash Configuration Register (FCNFG) CCIE, IGNSF, WSTAT, FDFD, and FSFD bits are readable and writable, ERSAREQ bit is read only, and remaining bits read 0 and are not writable. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 629 1 Flash array read operation will force the SFDIF flag in the FERSTAT register to be set (see Section 19.3.2.7) and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set (see Section 19.3.2.6) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 630 19.3.2.8) 1 An interrupt will be requested whenever the SFDIF flag is set (see Section 19.3.2.8) 19.3.2.7 Flash Status Register (FSTAT) The FSTAT register reports the operational status of the Flash module. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 631 Flash command. See Section 19.4.7, “Flash Command Description,” and Section 19.6, “Initialization” for details. 19.3.2.8 Flash Error Status Register (FERSTAT) The FERSTAT register reflects the error status of internal Flash operations. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 632 The FPROT register defines which P-Flash sectors are protected against program and erase operations. Offset Module Base + 0x0008 RNV6 FPOPEN FPHDIS FPHS[1:0] FPLDIS FPLS[1:0] Reset = Unimplemented or Reserved Figure 19-13. Flash Protection Register (FPROT) 1. Loaded from Flash configuration field, during reset sequence. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 633 Flash Protection Lower Address Size — The FPLS bits determine the size of the protected/unprotected area FPLS[1:0] in P-Flash memory as shown in Table 19-22. The FPLS bits can only be written to while the FPLDIS bit is set. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 634 Flash memory at global address 0xFF_FE0C during the reset sequence, it can be changed by the user. The P-Flash protection scheme can be used by applications requiring reprogramming in normal single chip mode while providing as much protection as possible if reprogramming is not required. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 635 FLASH START 0xFF_8000 0xFF_FFFF Protected region with size Unprotected region defined by FPLS Protected region Protected region with size not defined by FPLS, FPHS defined by FPHS Figure 19-14. P-Flash Protection Scenarios MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 636 During the reset sequence, fields DPOPEN and DPS of the DFPROT register are loaded with the contents of the EEPROM protection byte in the Flash configuration field at global address 0xFF_FE0D located in MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 637 EEPROM range can always be protected. Each DPS value increment increases the size of the protected range by 32-bytes. Thus to protect a 1 KB range DPS[4:0] must be set (protected range of 32 x 32 bytes). MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 638 All bits in the FRSV1 register read 0 and are not writable. 19.3.2.13 Flash Common Command Object Registers (FCCOB) The FCCOB is an array of six words. Byte wide reads and writes are allowed to the FCCOB registers. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 639 Offset Module Base + 0x000F CCOB[7:0] Reset Figure 19-21. Flash Common Command Object 1 Low Register (FCCOB1LO) Offset Module Base + 0x0010 CCOB[15:8] Reset Figure 19-22. Flash Common Command Object 2 High Register (FCCOB2HI) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 640 Offset Module Base + 0x0014 CCOB[15:8] Reset Figure 19-26. Flash Common Command Object 4 High Register (FCCOB4HI) Offset Module Base + 0x0015 CCOB[7:0] Reset Figure 19-27. Flash Common Command Object 4 Low Register (FCCOB4LO) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 641 Table 19-27. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] Register Byte FCCOB Parameter Fields (NVM Command Mode) FCMD[7:0] defining Flash command FCCOB0 Global address [23:16] Global address [15:8] FCCOB1 Global address [7:0] Data 0 [15:8] FCCOB2 Data 0 [7:0] MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 642: Functional Description
Reference Manual for details). Forcing the DFDF status bit by setting FDFD (see Section 19.3.2.5) has effect only on the DFDF status bit value and does not result in an invalid access. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 643: Internal Nvm Resource
Internal NVM resource IFR is an internal NVM resource readable by CPU. The IFR fields are shown in Table 19-5.. The NVM Resource Area global address map is shown in Table 19-6.. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 644: Flash Command Operations
Flash command has completed. Upon completion, the Memory Controller will return CCIF to 1 and the FCCOB register will be used to communicate any results. The flow for a generic command write sequence is shown in Figure 19-30. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 645 More Parameters? Write: FSTAT register (to launch command) Clear CCIF 0x80 Read: FSTAT register Bit Polling for Command Completion CCIF Set? Check EXIT Figure 19-30. Generic Flash Command Write Sequence Flowchart MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 646 Erase EEPROM Sector     0x13 Protection Override 1. Unsecured Normal Single Chip mode 2. Unsecured Special Single Chip mode. 3. Secured Normal Single Chip mode. 4. Secured Special Single Chip mode. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 647 Supports a mode to temporarily override Protection configuration (for P-Flash and/or 0x13 Override EEPROM) by verifying a key. 19.4.5.5 EEPROM Commands Table 19-31 summarizes the valid EEPROM commands along with the effects of the commands on the EEPROM block. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 648: Allowed Simultaneous P-Flash And Eeprom Operations
If more than one hardblock exists on a device, then read operations on one hardblock are permitted whilst program or erase operations are executed on the other hardblock. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 649: Flash Command Description
Cumulative programming of bits within a Flash word or phrase is not allowed. 19.4.7.1 Erase Verify All Blocks Command The Erase Verify All Blocks command will verify that all P-Flash and EEPROM blocks have been erased. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 650 P-Flash or EEPROM block is erased. The CCIF flag will set after the Erase Verify Block operation has completed.If the block is not erased, it means blank check failed, both MGSTAT bits will be set. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 651 Set if any errors have been encountered during the read or if blank check failed. Set if any non-correctable errors have been encountered during the read or if MGSTAT0 blank check failed. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 652 A P-Flash phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash phrase is not allowed. Table 19-41. Program P-Flash Command FCCOB Requirements Register FCCOB Parameters Global address [23:16] to FCCOB0 0x06 identify P-Flash block MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 653 FCCOB1 Program Once phrase index (0x0000 - 0x0007) FCCOB2 Program Once word 0 value FCCOB3 Program Once word 1 value FCCOB4 Program Once word 2 value FCCOB5 Program Once word 3 value MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 654 During the execution of this command (CCIF=0) the user must not write to any Flash module register. The CCIF flag will set after the Erase All Blocks operation has completed. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 655 Set if any errors have been encountered during the erase verify operation, or MGSTAT1 FSTAT during the program verify operation Set if any non-correctable errors have been encountered during the erase verify MGSTAT0 operation, or during the program verify operation MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 656 Upon clearing CCIF to launch the Erase P-Flash Sector command, the Memory Controller will erase the selected Flash sector and then verify that it is erased. The CCIF flag will be set after the Erase P-Flash Sector operation has completed. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 657 FSEC register (see Table 19-10.). The Verify Backdoor Access Key command releases security if user- supplied keys match those stored in the Flash security bytes of the Flash configuration field (see Table 19- MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 658 Table 19-56. Set User Margin Level Command FCCOB Requirements Register FCCOB Parameters Global address [23:16] to identify Flash FCCOB0 0x0D block FCCOB1 Global address [15:0] to identify Flash block FCCOB2 Margin level setting. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 659 19.4.7.13 Set Field Margin Level Command The Set Field Margin Level command, valid in special modes only, causes the Memory Controller to set the margin level specified for future read operations of the P-Flash or EEPROM block. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 660 Set if command not available in current mode (see Table 19-29) ACCERR Set if an invalid global address [23:0] is supplied see Table 19-3) FSTAT Set if an invalid margin level setting is supplied FPVIOL None MGSTAT1 None MGSTAT0 None MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 661 Set if any errors have been encountered during the read or if blank check failed. Set if any non-correctable errors have been encountered during the read or if MGSTAT0 blank check failed. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 662 Set if any non-correctable errors have been encountered during the verify MGSTAT0 operation 19.4.7.16 Erase EEPROM Sector Command The Erase EEPROM Sector operation will erase all addresses in a sector of the EEPROM block. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 663 Table 19-68. Protection Override Command FCCOB Requirements Register FCCOB Parameters Protection Update Selection FCCOB0 0x13 [1:0] See Table 19-69. FCCOB1 Comparison Key FCCOB2 reserved New FPROT value FCCOB3 reserved New DFPROT value MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 664 FPROT and/or DFPROT registers were modified by direct register writes while protection is overridden these modifications will be lost. Running Protection Override command to restore the contents of registers FPROT and DFPROT will not force them to the reset values. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 665: Interrupts
Error Configuration Register (FERCNFG)”, Section 19.3.2.7, “Flash Status Register (FSTAT)”, and Section 19.3.2.8, “Flash Error Status Register (FERSTAT)”. The logic used for generating the Flash module interrupts is shown in Figure 19-31. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 666: Wait Mode
Access Key command match the backdoor keys stored in the Flash memory, the SEC bits in the FSEC register (see Table 19-11) will be changed to unsecure the MCU. Key values of 0x0000 and 0xFFFF are MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 667: Unsecuring The Mcu In Special Single Chip Mode Using Bdm
If a double bit fault is detected during the reset sequence, both MGSTAT bits in the FSTAT register will be set. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 668 If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 669: A.1 General
Appendix A MCU Electrical Specifications General This supplement contains the most accurate electrical information for the MC9S12ZVMB-Family available at the time of publication. A.1.1 Parameter classification The electrical parameters shown in this supplement are guaranteed by various methods. The parameter classification is documented in the PPAP.
Page 670 VDDX may go out of regulation. Ensure the external V load will shunt current greater than maximum injection current. This is the greatest risk when the MCU is not consuming MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 671 Table A-2. Absolute maximum ratings Rating Symbol Unit Voltage regulator supply voltage -0.3 High side driver supply voltage -0.3 SUPHS DC voltage on LIN FET-Predriver High-Side Drain -0.3 FET-Predriver Bootstrap Capacitor Connection -0.3 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 672 ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 673 220pF capacitor (R=330, C=150pF): LIN versus LGND Latch-up Current of 5V GPIOs at T=125C positive +100 negative -100 Latch-up Current VCP, LIN, GHD, GHS[1:0], GHG[1:0], GLG[1:0], GLS[1:0], HS[1:0], PL[2:0] Tested at T=125C and T=150C positive +100 negative -100 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 674 4. Can be placed anywhere on the VLS node A.1.7 Operating conditions This section describes the operating conditions of the device. Unless otherwise noted these conditions apply to the following electrical parameters. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 675 T and device junction temperature T 4. Refer to f for minimum ADC operating frequency. This is derived from the bus clock. ATDCLK MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 676 SUPHS SUPHS = (-V ) + (V Power dissipation of FET-Predriver without the outputs VLS_OUT VLS_OUT ) + (V switching VLSn VLSn 1. No switching. GDU power consumption is very load dependent. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 677 Appendix A MCU Electrical Specifications Figure A-2. Supply currents overview MC9S12ZVMB-Family VBAT VSUP VLS_OUT BCTL VDDA VDDX VDDX VBS[1:0] VSSX EVDD GPIO EVDD Table A-8. Thermal Package Characteristics For 64LQFP Rating achieved by thermal simulations Symbol Unit  C/W Thermal resistance, single sided PCB Natural —...
Page 678 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 679: A.2 I/O Pin Characteristics
Internal pull up current (All GPIO except RESET) — -130 min > input voltage > V  Internal pull up resistance (RESET pin) A Internal pull down current — min > input voltage > V MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 680 1/f RESET pin input pulse filtered — — P_MASK RESET pin input pulse passed — — P_PASS 1. Parameter only applies in stop or pseudo stop mode. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 681: A.3 Supply Currents
+150°C the bus frequency is 32MHz. For the temperature range from +150°C to +175°C, the bus frequency is 25MHz. Table A-13, Table A-14 Table A-15 show the configuration of the CPMU module and the peripherals for Run, Wait and Stop current measurement. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 682 The module is disabled, as in typical final applications The module is configured with a modulus rate of 10 kHz The peripheral is configured to output compare mode, MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 683 1. If MCU is in STOP long enough then TA = TJ . Die self heating due to stop current is negligible Table A-18. Pseudo Stop Current Characteristics Conditions are: V =12V, API, COP & RTI enabled Rating Symbol Unit A = 25C — 270.0 399.6 SUPPS MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 684 Appendix A MCU Electrical Specifications MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 685: B.1 Vreg Electrical Specifications
Appendix B CPMU Electrical Specifications (VREG, OSC, IRC, PLL) VREG Electrical Specifications Table B-1. Voltage Regulator Electrical Characteristics (Junction Temperature From –40C To +175C) VDDA and VDDX must be shorted on the application board. Characteristic Symbol Typical Unit Input Voltages —...
Page 686: B.2 Reset And Stop Timing Characteristics
Unit Junction Temperature - 40 to 150 Celsius 0.9895 1.002 1.0145 IRC1M_TRIM Internal Reference Frequency, factory trimmed Junction Temperature 150 to 175 Celsius 0.9855 — 1.0145 IRC1M_TRIM Internal Reference Frequency, factory trimmed MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 687: B.4 Phase Locked Loop
Figure B-1. Jitter Definitions The relative deviation of t is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (N). Defining the jitter as: MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 688 Jitter fit parameter 1 C < T < 150 — —   Jitter fit parameter 1 150 C < T < 175 — — PLL Clock Monitor Failure assert frequency 0.45 PMFA MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 689 Appendix B CPMU Electrical Specifications (VREG, OSC, IRC, PLL) 1. % deviation from target frequency 2. f = 1MHz, f = 32 MHz MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 690 Appendix B CPMU Electrical Specifications (VREG, OSC, IRC, PLL) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 691: C.1 Adc Operating Characteristics
Factors Influencing Accuracy Source resistance, source capacitance and current injection have an influence on the accuracy of the ADC .Figure C-1. A further factor is PortAD pins that are configured as output drivers switching. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 692 4. Similarly, when the ADC is converting an HVI pin voltage, then the impedance converter bypass must be disabled to ensure that current injection on PADx pins does not impact the HVI ADC conversion result. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 693 Cstray < 1.8pF VSSA (incl parasitics) bottom connected to low ohmic supply during sampling Switch resistance depends on input voltage, corner ranges are shown. Leakage current is guaranteed by specification. =150 jmax Figure C-1. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 694 -------------------------- - 1 – 1LSB The integral non-linearity (INL) is defined as the sum of all DNLs: –  INL n   DNL i   -------------------- - n – 1LSB MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 695 $3FC $3FB $3FA $3F9 $3F8 $3F7 $3F6 $3F5 $3F4 $3F3 Ideal Transfer Curve 10-Bit Transfer Curve 8-Bit Transfer Curve 95 100 105 110 115 120 5000 + Figure C-2. ADC Accuracy Definitions MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 696 1. ADC values are characterized over the range 4.5 V < V < 5.5 V. Production test uses 4.85 V < V < 5.15 V. 2. The 8-bit mode operation is structurally tested in production test. Absolute values are tested in 10-bit mode. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 697: D.1 Maximum Ratings
Receiver recessive state LINrec LINSUP 0.475 0.525 LIN_CNT th_dom th_rec LIN_CNT LINSUP 0.175 th_rec th_dom LINSUP Maximum capacitance allowed on slave node including slave external components Capacitance of the LIN pin, Recessive state MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 698: D.3 Dynamic Electrical Characteristics
= 50us D2 = t / (2 x t Bus_rec(max) LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4KBIT/S s Rising/falling edge time (min to max / max to min) rise MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 699 D2 and D4 which may increase and potentially go beyond their maximum limits for highly loaded buses. 3. The V voltage is provided by the VLINSUP supply. This supply mapping is described in device level documen- LINSUP tation. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 700 Appendix D LINPHY Electrical Specifications MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 701: E.1 Operating Characteristics
< 150C GHG/GLG turn off time vs 10nF load HGOFF 150C < T < 175C s PMF control to GHG/GLG start of turn on delay 0.508 0.682 0.742 delon (fastest slew, TDEL=1) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 702 Current Sense Amplifier large signal settling time — — cslsst Current Sense Amplifier unity gain bandwidth — — (12) Current Sense Amplifier input resistance — — — —  s Over Current Comparator filter time constant MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 703 7. The variation on a given device for a given slew setting is much less than the specified range. 8. V(VBSx) - V(VLSx) > 9V, resp VLSx > 9V 9. V(VBSx) - V(VLSx) > 9V, resp VLSx > 9V, nmos branch only MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 704 12. Input resistance can be calculated from the pin input leakage because the sense amp has high impedance MOS inputs 13. Low side desaturation comparator range extends to LSx <= 2.35V - V desatls MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 705: F.1 Operating Characteristics
In such cases of capacitive loads you can leverage the over current masking feature or handle it by software. Nominal Current for continuous operation. – – NOMHSX This value is valid for each HS-driver output. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 706 Leakage Current -40°C < T < 175°C – µA LEAK_UH (0V < V < V HS0/1 SUP_HS A High-Load Resistance Open-Load Detection Current – – HLROLDC (if High-side driver is enabled and gate turned off) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 707: F.3 Dynamic Characteristics
Over-Current Shutdown Masking Time(IRC trimmed at HSOCM 1 MHz) s High-Load Resistance Open-Load Detection Switch On – – HLROLOT Time s High-Load Resistance Open-Load Detection Time – – HLROLDT (capacitive load = 50pF) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 708 Appendix F HSDRV Electrical Specifications MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 709: G.1 Nvm Timing Parameters
All timing parameters are a function of the bus clock frequency, f . All NVMBUS program and erase times are also a function of the NVM operating frequency, f . A summary of key NVMOP timing parameters can be found in Table G-1. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 710: G.2 Nvm Reliability Parameters
NVMOP NVMBUS NVM Reliability Parameters The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 711: G.3 Nvm Factory Shipping Condition
Devices are shipped from the factory with flash and EEPROM in the erased state. Data retention specifications begin at time of this erase operation. For additional information on how Freescale defines Typical Data Retention, please refer to Engineering Bulletin EB618. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 712 Appendix G NVM Electrical Specifications MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 713: H.1 Static Electrical Characteristics
Analog Input Matching – +-2% +-5% – Matching Absolute Error on V - compared to V / Ratio VSUP 1. T : Ambient Temperature 2. V : Voltage accessible at the ADC input channel MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 714: H.2 Dynamic Electrical Characteristics
T = 25°C under nominal conditions.. Ratings Symbol Unit Enable Uncertainty Time – – EN_UNC Voltage Warning Low Pass Filter – – VWLP_filter 1. T : Ambient Temperature MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 715: I.1 Master Mode
2. LSBFE = 0. For LSBFE = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure I-2. SPI Master Timing (CPHA=0) In Figure I-3. the timing diagram for master mode with transmission format CPHA=1 is depicted. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 716 Data Valid after SS fall (CPHA=0) — — Data Hold Time (Outputs) — — Rise and Fall Time Inputs — — Rise and Fall Time Outputs — — 1. pls. see Figure I-4. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 717 BIT 6 . . . 1 SLAVE LSB OUT SLAVE MSB (OUTPUT) note note MOSI BIT 6 . . . 1 MSB IN LSB IN (INPUT) NOTE: Not defined! Figure I-5. SPI Slave Timing (CPHA=0) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 718 — — 0.5 t Data Hold Time (Outputs) — — Rise and Fall Time Inputs — — Rise and Fall Time Outputs — — 1. 0.5t added due to internal synchronization delay MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 719: Mc9S12Zvmb Family Reference Manual Rev. 1.3 Nxp Semiconductors
Appendix J Package Information Appendix J Package Information 64LQFP Package Mechanical Information Figure J-1. 64LQFP Mechanical Information (1 of 3) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 720 Appendix J Package Information Figure J-2. 64LQFP Mechanical Information (2 of 3) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 721 Appendix J Package Information Figure J-3. 64LQFP Mechanical Information (3 of 3) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 722: J.2 48Lqfp Package Mechanical Information
Appendix J Package Information 48LQFP Package Mechanical Information Figure J-4. 48LQFP Mechanical Information (1 of 2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 723 Appendix J Package Information Figure J-5. 48LQFP Mechanical Information (2 of 2) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 724: Appendix K
V = MagniV Family Main Memory Type: 9 = Flash Status / Partnumber type: S or SC = Maskset specific partnumber MC = Generic / mask-independent partnumber P or PC = prototype status (pre qualification) MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 725: L.1 0X0000–0X0003 Part Id
Appendix L Detailed Register Address Map Appendix L Detailed Register Address Map The following tables show the detailed register map. NOTE Smaller derivatives of the MC9S12ZVMB-Family feature a subset of the listed modules. 0x0000–0x0003 Part ID Address Name Bit 7...
Page 726 Appendix L Detailed Register Address Map 0x0010–0x001F S12ZINT Address Name Bit 7 Bit 0 0x001E INT_CFDATA6 PRIOLVL[2:0] 0x001F INT_CFDATA7 PRIOLVL[2:0] MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 727: L.3 0X0070-0X00Ff S12Zmmc
MMCPCH CPUPC[23:16] 0x0086 MMCPCM CPUPC[15:8] 0x0087 MMCPCL CPUPC[7:0] 0x0088- Reserved 0x00FF 0x0100-0x017F S12ZDBG Address Name Bit 7 Bit 0 0x0100 DBGC1 reserved BDMBP BRKCPU reserved EEVE1 TRIG 0x0101 DBGC2 ABCM 0x0102 Reserved MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 728 DBGAAH DBGAA[23:16] 0x0116 DBGAAM DBGAA[15:8] 0x0117 DBGAAL DBGAA[7:0] 0x0118 DBGAD0 Bit 31 Bit 24 0x0119 DBGAD1 Bit 23 Bit 16 0x011A DBGAD2 Bit 15 Bit 8 0x011B DBGAD3 Bit 7 Bit 0 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 729 0x0125 DBGBAH DBGBA[23:16] 0x0126 DBGBAM DBGBA[15:8] 0x0127 DBGBAL DBGBA[7:0] 0x0128- Reserved 0x013F 0x0140 DBGDCTL INST reserved COMPE 0x0141- Reserved 0x0144 0x0145 DBGDAH DBGDA[23:16] 0x0146 DBGDAM DBGDA[15:8] 0x0147 DBGDAL DBGDA[7:0] 0x0148- Reserved 0x017F MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 730 Reserved 0x020C 0x020D Reserved Reserved Reserved 0x020E Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x020F Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x0210– Reserved 0x025F 0x0260 PTE1 PTE0 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 731 PTADL1 PTADL0 PTIADH0 0x0282 PTIADH R PTIADL7 PTIADL6 PTIADL5 PTIADL4 PTIADL3 PTIADL2 PTIADL1 PTIADL0 0x0283 PTIADL 0x0284 DDRADH DDRADH0 0x0285 DDRADL DDRADL7 DDRADL6 DDRADL5 DDRADL4 DDRADL3 DDRADL2 DDRADL1 DDRADL0 0x0286 PERADH PERADH0 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 732 PTT1 PTT0 PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 0x02C1 PTIT 0x02C2 DDRT DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 0x02C3 PERT PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 733 RDRT2 0x02CE– Reserved 0x02CF 0x02D0– Reserved 0x02EF 0x02F0 PTP1 PTP0 PTIP1 PTIP0 0x02F1 PTIP 0x02F2 DDRP DDRP1 DDRP0 0x02F3 PERP PERP1 PERP0 0x02F4 PPSP PPSP1 PPSP0 0x02F5 Reserved 0x02F6 PIEP PIEP1 PIEP0 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 734 0x02FE– Reserved 0x02FF 0x0300– Reserved 0x032F 0x0330 Reserved PTIL2 PTIL1 PTIL0 0x0331 PTIL 0x0332 Reserved 0x0333 PTPSL PTPSL2 PTPSL1 PTPSL0 0x0334 PPSL PPSL2 PPSL1 PPSL0 0x0335 Reserved 0x0336 PIEL PIEL2 PIEL1 PIEL0 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 735: L.6 0X0380-0X039F Ftmrz
FDIV0 KEYEN1 KEYEN0 RNV5 RNV4 RNV3 RNV2 SEC1 SEC0 0x0381 FSEC 0x0382 FCCOBIX CCOBIX2 CCOBIX1 CCOBIX0 WSTATAC R FPOVRD 0x0383 FPSTAT ERSAREQ 0x0384 FCNFG CCIE IGNSF WSTAT[1:0] FDFD FSFD 0x0385 FERCNFG SFDIE MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 736 CCOB1 CCOB0 0x0394 FCCOB4HI CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 0x0395 FCCOB4LO CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 0x0396 FCCOB5HI CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 737: L.7 0X03C0-0X03Cf Sram_Ecc_32D7P
SBEEIF 0x03C3 - Reserved 0x03C6 0x03C7 ECCDPTRH DPTR[23:16] 0x03C8 ECCDPTRM DPTR[15:8] 0x03C9 ECCDPTRL DPTR[7:1] 0x03CA - Reserved 0x03CB 0x03CC ECCDDH DDATA[15:8] 0x03CD ECCDDL DDATA[7:0] 0x03CE ECCDE DECC[5:0] 0x03CF ECCDCMD ECCDRR ECCDW ECCDR MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 738: L.8 0X0400-0X042F Tim1
EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A 0x040C TIM1TIE 0x040D TIM1TSCR2 0x040E TIM1TFLG1 0x040F TIM1TFLG2 0x0410 TIM1TC0H Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 739 0x041F 0x0420 Reserved 0x0421 Reserved 0x0422 Reserved 0x0423 Reserved 0x0424– Reserved 0x042B 0x042C TIM1OCPD OCPD3 OCPD2 OCPD1 OCPD0 0x042D Reserved 0x042E TIM1PTPSR PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 0x042F Reserved MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 740: L.9 0X0500-X053F Pmf15B6C
Reserved 0x050B 0x050C PMFOUTC OUTCTL5 OUTCTL4 OUTCTL3 OUTCTL2 OUTCTL1 OUTCTL0 0x050D PMFOUTB OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 0x050E PMFDTMS 0x050F PMFCCTL ISENS IPOLC IPOLB IPOLA 0x0510 PMFVAL0 PMFVAL0 0x0511 PMFVAL0 PMFVAL0 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 741 0x051E PMFICCTL PECC PECB PECA ICCC ICCB ICCA 0x051F PMFCINV CINV5 CINV4 CINV3 CINV2 CINV1 CINV0 0x0520 PMFENCA PWMENA GLDOKA RSTRTA LDOKA PWMRIEA 0x0521 PMFFQCA LDFQA HALFA PRSCA PWMRFA PMFCNTA 0x0522 PMFCNTA MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 742 PWMRFB PMFCNTB 0x052A PMFCNTB PMFCNTB 0x052B PMFCNTB 0x052C PMFMODB PMFMODB 0x052D PMFMODB PMFMODB 0x052E PMFDTMB PMFDTMB 0x052F PMFDTMB PMFDTMB 0x0530 PMFENCC PWMENC GLDOKC RSTRTC LDOKC PWMRIEC 0x0531 PMFFQCC LDFQC HALFC PRSCC PWMRFC MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 743: L.10 0X0580-0X059F Ptu
DMP40 0x053D PMFDMP5 DMP55 DMP54 DMP53 DMP52 DMP51 DMP50 0x053E PMFOUTF OUTF5 OUTF4 OUTF3 OUTF2 OUTF1 OUTF0 0x053F Reserved L.10 0x0580-0x059F PTU Address Name Bit 7 Bit 0 0x0580 PTUE PTUFRZ TG0EN MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 744 0x0586 TG0LIST TG0TNUM[4:0] 0x0587 TG0TNUM TG0TV[15:8] 0x0588 TG0TVH TG0TV[7:0] 0x0589 TG0TVL 0x058A - Reserved 0x058D PTUCNT[15:8] 0x058E PTUCNTH PTUCNT[7:0] 0x058F PTUCNTL 0x0590 Reserved 0x0591 PTUPTRH PTUPTR[23:16] 0x0592 PTUPTRM PTUPTR[15:8] 0x0593 PTUPTRL PTUPTR[7:1] MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 745: L.11 0X05C0-0X05Ef Tim0
TCNT3 TCNT2 TCNT1 TCNT0 0x05C6 TIM0TSCR1 TSWAI TSFRZ TFFCA PRNT 0x05C7 TIM0TTOV TOV3 TOV2 TOV1 TOV0 0x05C8 Reserved 0x05C9 TIM0TCTL2 0x05CA Reserved 0x05CB TIM0TCTL4 EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 746 Bit 2 Bit 1 Bit 0 0x05D8- Reserved 0x05DF 0x05E0- Reserved 0x05EB 0x05EC TIM0OCPD OCPD3 OCPD2 OCPD1 OCPD0 0x05ED Reserved 0x05EE TIM0PTPSR PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 0x05EF Reserved MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 747: L.12 0X0600-0X063F Adc0
0x060E ADC0IMDRI_0 RIDX_IMD[5:0] 0x060F ADC0IMDRI_1 R CSL_EOL RVL_EOL 0x0610 ADC0EOLRI 0x0611 Reserved 0x0612 Reserved R Reserved Reserved 0x0613 Reserved 0x0614 ADC0CMD_0 CMD_SEL OPT[1:0] INTFLG_SEL[3:0] 0x0615 ADC0CMD_1 VRH_SEL[1:0] CH_SEL[5:0] 0x0616 ADC0CMD_2 SMP[4:0] OPT[3:2] Reserved MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 748: L.13 0X06A0-0X06Bf Gdu
Reserved 0x0627- Reserved Reserved 0x063F L.13 0x06A0-0x06BF GDU Address Name Bit 7 Bit 0 0x06A0 GDUE GOVA GCSE0 GCPE GFDE 0x06A1 GDUCTR GHHDLVL GVLSLVL GBKTIM2[3:0] GBKTIM1[1:0] GOCIE0 0x06A2 GDUIE GDSEIE GHHDIE GLVLSIE MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 749 0x06A9 GDUPHMUX GPHMX[1:0] 0x06AA GDUCSO GCSO0[2:0] 0x06AB GDUDSLVL GDSFHS GDSLHS[2:0] GDSFLS GDSLLS[2:0] GPHL[1:0] 0x06AC GDUPHL 0x06AD GDUCLK2 GCPCD[3:0] 0x06AE GDUOC0 GOCA0 GOCE0 GOCT0[4:0] 0x06AF Reserved 0x06B0 GDUCTR1 GBSWOFF[1:0] TDEL 0x06B1- Reserved 0x06BF MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 750: L.14 0X06C0-0X06Df Cpmu
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HTDS CPMU 0x06D0 ATEMPEN VSEL HTIE HTIF HTCTL LVDS CPMU 0x06D1 LVIE LVIF LVCTL CPMU 0x06D2 APICLK APIES APIEA APIFE APIE APIF APICTL MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 751: L.15 0X06F0-0X06F7 Bats
CPMUOSC2 OMRE OSCMOD 0x06DF RESERVED L.15 0x06F0-0x06F7 BATS Address Name Bit 7 Bit 0 0x06F0 BATE BVHS BVLS[1:0] BSUAE BSUSE BVHC BVLC 0x06F1 BATSR 0x06F2 BATIE BVHIE BVLIE 0x06F3 BATIF BVHIF BVLIF MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 752: L.16 0X0700-0X0707 Sci0
1 These registers are accessible if the AMAP bit in the SCISR2 register is set to zero. 2 These registers are accessible if the AMAP bit in the SCISR2 register is set to one. MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 753: L.17 0X0710-0X0717 Sci1
Bit 0 Name 0x0780 SPI0CR1 SPIE SPTIE MSTR CPOL CPHA SSOE LSBFE 0x0781 SPI0CR2 XFRW MODFEN BIDIROE SPISWAI SPC0 0x0782 SPI0BR SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 SPIF SPTEF MODF 0x0783 SPI0SR MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 754: L.19 0X0980-0X0987 Linphy0
LPOCIE 0x0987 LP0IF LPDTIF LPOCIF L.20 0x09C0-0x09C7 HSDRV0 Address Name Bit 7 Bit 0 0x09C0 HSDR HSDR1 HSDR0 HSOC- HSOC- 0x09C1 HSCR HSOLE1 HSOLE0 HSE1 HSE0 0x09C2 HSSLR HSSLCU1 HSSLCU0 HSSLEN1 HSSLEN0 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 755 L.20 0x09C0-0x09C7 HSDRV0 Address Name Bit 7 Bit 0 0x09C3 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x09C4 Reserved HSOL1 HSOL0 0x09C5 HSSR 0x09C6 HSIE HSOCIE 0x09C7 HSIF HSOCIF1 HSOCIF0 MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 756 Appendix L Detailed Register Address Map MC9S12ZVMB Family Reference Manual Rev. 1.3 NXP Semiconductors...
Page 757 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right Home Page: to make changes without further notice to any products herein.
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NXP Semiconductors MC9S12ZVMB-Family Reference Manual

Chapter 1 ADC Module Versions

Chapter 2

Chapter 3

Chapter 6

Chapter 4

Chapter 5

Chapter 7

Chapter 8

Chapter 9

Chapter 10

Chapter 11

Chapter 12

Chapter 18

Chapter 14

Chapter 15

Chapter 16

Chapter 17 Memory Map and Register Definition

Chapter 19

Appendix A

Appendix B

Appendix C

Appendix D

Appendix E

Appendix F

Appendix G

Appendix H

Appendix I Appendix K

Appendix L

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