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Functional description
After I2C address matching wake-up, the master must wait a
time long enough for the slave ISR to finish running and resend
start or repeat start signals.
For the SRW bit to function properly, it only supports Address
+Write to wake up by I2C address matching. Before entering
the next low power mode, Address+Write must be sent to
change the SRW status.
21.5.8 Double buffering mode
In the double buffering mode, the data transfer is processed byte by byte. However, the
data can be transferred without waiting for the interrupt or the polling to finish. This
means the write/read I2C_D operation will not block the data transfer, as the hardware
has already finished the internal write or read. The benefit is that the baud rate is able to
achieve higher speed.
There are several items to consider as follows:
• When initiating a double buffering transfer at Tx side, the user can write 2 values to
the I2C_D buffer before transfer. However, that is allowed only at one time per
package frame (due to the buffer depth, and because two-times writes in each ISR are
not allowed). The second write to the I2C_D buffer must wait for the Empty flag. On
the other hand, at Rx side the user can read twice in a one-byte transfer (if needed).
Check Empty flag before write to I2C_D.
Write twice to the I2C_D buffer ONLY after the address
matching byte. Do not write twice (Address+Data) before
START or at the beginning of I2C transfer, especially when
the baud rate is very slow.
• To write twice in one frame, during the next-to-last ISR, do a dummy read from the
I2C_D buffer at Tx side (or the TCF will stay high, because the TCF is cleared by
write/read operation). In the next-to-last ISR, do not send data again (the buffer data
will be under running).
• To keep new ISRs software-compatible with previous ISRs, the write/read I2C_D
operation will not block the internal-hardware-released SCL/SDA signals. At the
390
NOTE
NOTE
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
NXP Semiconductors
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