Phcmp0 Control Register 0 (Gdu_Phcmp0Cr0) - NXP Semiconductors MC9S08SU16 Reference Manual

25.6.1 PHCMP0 Control Register 0 (GDU_PHCMP0CR0)

Address: 20h base + 0h offset = 20h
Bit 7
Read 0
Write
Reset
0
Field
7 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
6–4 Filter Sample Count
FILTER_CNT
These bits represent the number of consecutive samples that must agree prior to the comparator ouput
filter accepting a new output state. For information regarding filter programming and latency reference the
Functional Description.
000 Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not
recommended). If SE = 0, COUT = COUTA.
001 1 consecutive sample must agree (comparator output is simply sampled).
010 2 consecutive samples must agree.
011 3 consecutive samples must agree.
100 4 consecutive samples must agree.
101 5 consecutive samples must agree.
110 6 consecutive samples must agree.
111 7 consecutive samples must agree.
3–1 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
0 Comparator hard block hysteresis control
HYSTCTR
Defines the programmable hysteresis level. The hysteresis values associated with each level is device-
specific. See the device's data sheet for the exact values.
0 Level 0
1 Level 1
25.6.2 PHCMP0 Control Register 1 (GDU_PHCMP0CR1)
Address: 20h base + 1h offset = 21h
Bit 7
Read
SE
Write
Reset
0
NXP Semiconductors
6 5
FILTER_CNT
0 0
GDU_PHCMP0CR0 field descriptions
6 5
0
WE PMODE
0 0
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
4 3
0 0
Description
4 3
INV COS
0 0
Chapter 25 Gate Drive Unit (GDU)
2 1
0
HYSTCTR
0 0
2 1
OPE EN
0 0
0
0
0
0
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