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Application information
When available on a separate pin, V
V
, or may be driven by an external source between the minimum V
DDA
V
potential (V
DDA
REFH
V
must be connected to the same voltage potential as V
REFL
be routed carefully for maximum noise immunity and bypass capacitors placed as near as
possible to the package.
AC current in the form of current spikes required to supply charge to the capacitor array
at each successive approximation step is drawn through the V
best external component to meet this current demand is a 0.1 µF capacitor with good high
frequency characteristics. This capacitor is connected between V
must be placed as near as possible to the package pins. Resistance in the path is not
recommended because the current causes a voltage drop that could result in conversion
errors. Inductance in this path must be minimum (parasitic only).
17.7.1.3 Analog input pins
The external analog inputs are typically shared with digital I/O pins on MCU devices.
The pin I/O control is disabled by setting the appropriate control bit in one of the pin
control registers. Conversions can be performed on inputs without the associated pin
control register bit set. It is recommended that the pin control register bit always be set
when using a pin as an analog input. This avoids problems with contention because the
output buffer is in its high impedance state and the pullup is disabled. Also, the input
buffer draws DC current when its input is not at V
register bits for all pins used as analog inputs should be done to achieve lowest operating
current.
Empirical data shows that capacitors on the analog inputs improve performance in the
presence of noise or when the source impedance is high. Use of 0.01 µF capacitors with
good high-frequency characteristics is sufficient. These capacitors are not necessary in all
cases, but when used they must be placed as near as possible to the package pins and be
referenced to V
.
SSA
For proper conversion, the input voltage must fall between V
is equal to or exceeds V
12-bit representation), 0x3FF (full scale 10-bit representation) or 0xFF (full scale 8-bit
representation). If the input is equal to or less than V
to 0x000. Input voltages between V
There is a brief current associated with V
The input is sampled for 3.5 cycles of the ADCK source when ADC_SC3[ADLSMP] is
low, or 23.5 cycles when ADC_SC3[ADLSMP] is high.
284
may be connected to the same potential as
REFH
must never exceed V
, the converter circuit converts the signal to 0xFFF (full scale
REFH
and V
REFH
REFL
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
). When available on a separate pin,
DDA
. V
SSA
REFH
or V
. Setting the pin control
DD
SS
REFH
, the converter circuit converts it
REFL
are straight-line linear conversions.
REFL
when the sampling capacitor is charging.
spec and the
DDA
and V
must
REFH
REFL
and V
loop. The
REFL
and V
and
REFH
REFL
and V
. If the input
REFL
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