Pulse Width Timer Control And Status Register (Pwtx_Cs) - NXP Semiconductors MC9S08SU16 Reference Manual

Absolute
address
(hex)
Pulse Width Timer Negative Pulse Width Register: High
34
(PWT0_NPH)
Pulse Width Timer Negative Pulse Width Register: Low
35
(PWT0_NPL)
36 Pulse Width Timer Counter Register: High (PWT0_CNTH)
37 Pulse Width Timer Counter Register: Low (PWT0_CNTL)
38 Pulse Width Timer Control and Status Register (PWT1_CS)
39 Pulse Width Timer Control Register (PWT1_CR)
Pulse Width Timer Positive Pulse Width Register: High
3A
(PWT1_PPH)
Pulse Width Timer Positive Pulse Width Register: Loq
3B
(PWT1_PPL)
Pulse Width Timer Negative Pulse Width Register: High
3C
(PWT1_NPH)
Pulse Width Timer Negative Pulse Width Register: Low
3D
(PWT1_NPL)
3E Pulse Width Timer Counter Register: High (PWT1_CNTH)
3F Pulse Width Timer Counter Register: Low (PWT1_CNTL)

20.4.1 Pulse Width Timer Control and Status Register (PWTx_CS)

Address: Base address + 0h offset
Bit 7
Read
PWTEN
Write
Reset
0
Field
7 PWT Module Enable
PWTEN
Enables/disables the PWT module. To avoid unexpected behavior, do not change any PWT configurations
as long as PWTEN is set.
0 The PWT is disabled.
1 The PWT is enabled.
6 PWT Module Interrupt Enable
PWTIE
Enables the PWT module to generate an interrupt.
0 Disables the PWT to generate interrupt.
1 Enables the PWT to generate interrupt.
NXP Semiconductors
PWT memory map (continued)
Register name
6 5
PWTIE PRDYIE
0 0
PWTx_CS field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 20 Pules Width Timer (PWT)
Width
(in bits)
8
8
8
8
8
8
8
8
8
8
8
8
4 3
0
POVIE
PWTSR
0 0
Description
Section/
Access Reset value
R 00h 20.4.5/350
R 00h 20.4.6/351
R 00h 20.4.7/351
R 00h 20.4.8/351
R/W 00h 20.4.1/347
R/W 00h 20.4.2/348
R 00h 20.4.3/349
R 00h 20.4.4/350
R 00h 20.4.5/350
R 00h 20.4.6/351
R 00h 20.4.7/351
R 00h 20.4.8/351
2 1
FCTLE PWTRDY PWTOV
0 0
page
0
0
347