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Module
System integration module (SIM)
Power management controller (PMC)
Development support
Debug module (DBG)
2.2.3 Memories and memory interfaces
The following memories and memory interfaces are available on this device.
Module
Flash memory
SRAM
System register file
2.2.4 Clocks
The following clock modules are available on this device.
Module
Internal Clock Source (ICS)
Low-Power Oscillator (LPO)
NXP Semiconductors
Table 2-3. System modules
The SIM includes integration logic and several module configuration settings.
The PMC provides the user with multiple power options. Multiple modes are
supported that allow the user to optimize power consumption for the level of
functionality needed. Includes power-on-reset (POR) and integrated low voltage
detect (LVD) with reset (brownout) capability and selectable LVD trip points.
Development supports single-wire background debug mode (BDM), which uses the
on-chip background debug controller (BDC) module, and the independent on-chip
realtime in-circuit emulation (ICE) system, which uses the on-chip debug (DBG)
module.
The DBG module implements an on-chip ICE (in-circuit emulation) system and
allows non-intrusive debug of application software by providing an on-chip trace
buffer with flexible triggering capability.
Table 2-4. Memories and memory interfaces
Program flash memory — up to 16 KB (SU16) or 8 KB (SU8) of the non-volatile
flash memory that can execute program code.
Up to 768 bytes internal system RAM, including 256 B of which is unrestricted, the
rest 512 B is restricted during flash erasing and programming.
Up to 8 bytes.
Table 2-5. Clock modules
ICS module containing an internal reference clock (ICSIRCLK) and a frequency
locked loop (FLL).
The PMC module contains a 20 kHz low-power oscillator which acts as a
standalone low-frequency clock source in all modes.
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 2 Introduction
Description
Description
Description
37
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