NXP Semiconductors MC9S08SU16 Reference Manual page 78

Pinout
24 Chip Module
QFN signal
name
TCLK MTIM
PTB6 PORT
10 CMP_REF/
VREFH
PWM_FAU PWM
LT0
CLK_IN
PTC0 PORT
11 BKGD/MS Core
CLKOUT SIM
PTB7 PORT
12 PWT1 PWT
TX SCI
XB_OUT1 XBAR
PTA7/ KBI7 PORT/K
BI
78
Table 7-1. Pin signal description (continued)
Module Operating
signal name voltage
range (V)
TCLK
PTB6
0–5
FAULT0
PTC0
BKGD/MS 0–5
CLKOUT
PTB7
PWT1IN0 0–5
TxD
XBAR_OUT1
PTA7/KBIP7
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Alt Type State
1
function during
reset
pullup
enabled
ALT2 I
ALT3 I/O
Default S Input
ALT1 I
ALT2 I
ALT3 I/O
Default I/O BKGD/MS Background / Mode Select
ALT2 O
ALT3 O
Default I Tri-State
ALT1 I/O
ALT2 O
ALT3 I/O
Signal description
asserted low, the device is
initialized and placed in the
reset state. A Schmitt-trigger
input is used for noise
immunity.
An optional external clock
source for the FTM, MTIM,
PWT0 and PWT1 modules.
The TCLK must be limited to
1/4th frequency of the bus
clock for synchronization.
This GPIO pin can be
individually programmed as an
input or output pin.
CMP_REF: Common input of
GDU Phase comparator A, B
and C; VREFH: On-chip 4.2V
Voltage reference output.
When this pin is configured as
VREFH, Connect a 2.2 µF
bypass capacitor between this
pin and VSS to stabilize the
voltage reference output
required for proper device
operation.
PWM fault input is used for
disabling selected PWM
outputs in case where fault
conditions originate off-chip
An optional external clock
source. This clock input cannot
be dynamically switched
between its inputs (DC - 40
MHz)
This GPIO pin can be
individually programmed as an
input or output pin.
A buffered bus clock output
This GPIO pin is an output pin
only.
Input 0 of PWT1
SCI transmit data output
Crossbar module output 1
This GPIO pin can be
individually programmed as an
input or output pin with KBI
functionality
NXP Semiconductors