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Chapter 27
Development support
27.1 Introduction
This chapter describes the single-wire background debug mode (BDM), which uses the
on-chip background debug controller (BDC) module, and the independent on-chip real-
time in-circuit emulation (ICE) system, which uses the on-chip debug (DBG) module.
27.1.1 Forcing active background
The method for forcing active background mode depends on the specific HCS08
derivative. For the 9S08xxxx, you can force active background after a power-on reset by
holding the BKGD pin low as the device exits the reset condition. You can also force
active background by driving BKGD low immediately after a serial background
command that writes a one to the BDFR bit in the SBDFR register. Other causes of reset
including an external pin reset or an internally generated error reset ignore the state of the
BKGD pin and reset into normal user mode. If no debug pod is connected to the BKGD
pin, the MCU will always reset into normal operating mode.
27.1.2 Features
Features of the BDC module include:
• Single pin for mode selection and background communications
• BDC registers are not located in the memory map
• SYNC command to determine target communications rate
• Non-intrusive commands for memory access
• Active background mode commands for CPU register access
• GO and TRACE1 commands
• BACKGROUND command can wake CPU from stop or wait modes
• One hardware address breakpoint built into BDC
NXP Semiconductors
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
529
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