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Register definition
Field
7
Loop Mode Select
LOOPS
Selects between loop back modes and normal 2-pin full-duplex modes. When LOOPS is set, the
transmitter output is internally connected to the receiver input.
0
Normal operation - RxD and TxD use separate pins.
1
Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input.
(See RSRC bit.) RxD pin is not used by SCI.
6
SCI Stops in Wait Mode
SCISWAI
0
SCI clocks continue to run in wait mode so the SCI can be the source of an interrupt that wakes up the
CPU.
1
SCI clocks freeze while CPU is in wait mode.
5
Receiver Source Select
RSRC
This bit has no meaning or effect unless the LOOPS bit is set to 1. When LOOPS is set, the receiver input
is internally connected to the TxD pin and RSRC determines whether this connection is also connected to
the transmitter output.
0
Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the SCI does not use
the RxD pins.
1
Single-wire SCI mode where the TxD pin is connected to the transmitter output and receiver input.
4
9-Bit or 8-Bit Mode Select
M
0
Normal - start + 8 data bits (lsb first) + stop.
1
Receiver and transmitter use 9-bit data characters start + 8 data bits (lsb first) + 9th data bit + stop.
3
Receiver Wakeup Method Select
WAKE
0
Idle-line wakeup.
1
Address-mark wakeup.
2
Idle Line Type Select
ILT
Setting this bit to 1 ensures that the stop bits and logic 1 bits at the end of a character do not count toward
the 10 or 11 bit times of logic high level needed by the idle line detection logic.
0
Idle character bit count starts after start bit.
1
Idle character bit count starts after stop bit.
1
Parity Enable
PE
Enables hardware parity generation and checking. When parity is enabled, the most significant bit (msb) of
the data character, eighth or ninth data bit, is treated as the parity bit.
0
No hardware parity generation or checking.
1
Parity enabled.
0
Parity Type
PT
Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total number
of 1s in the data character, including the parity bit, is odd. Even parity means the total number of 1s in the
data character, including the parity bit, is even.
0
Even parity.
1
Odd parity.
402
SCIx_C1 field descriptions
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
NXP Semiconductors
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