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STACKING
ORDER
When an RTI instruction executes, these values are recovered from the stack in reverse
order. As part of the RTI sequence, the CPU fills the instruction pipeline by reading three
bytes of program information, starting from the PC address recovered from the stack.
The status flag causing the interrupt must be acknowledged (cleared) before returning
from the ISR. Typically, the flag must be cleared at the beginning of the ISR because if
another interrupt is generated by this source it will be registered so that it can be serviced
after completion of the current ISR.
4.1.2 Hardware nested interrupt
This device has interrupt priority controller (IPC) module to provide up to four-level
nested interrupt capability. IPC includes the following features:
• Four-level programmable interrupt priority for each interrupt source.
• Support for prioritized preemptive interrupt service routines
• Low-priority interrupt requests are blocked when high-priority interrupt service
routines are being serviced.
• Higher or equal priority level interrupt requests can preempt lower priority
interrupts being serviced.
• Automatic update of interrupt priority mask with being serviced interrupt source
priority level when the interrupt vector is being fetched.
NXP Semiconductors
UNSTACKING
ORDER
7
5
1
CONDITION CODE REGISTER
4
2
ACCUMULATOR
INDEX REGISTER (LOW BYTE X)
3
3
4
2
PROGRAM COUNTER HIGH
1
5
PROGRAM COUNTER LOW
* High byte (H) of index register is not automatically stacked.
Figure 4-1. Interrupt stack frame
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
TOWARD LOWER ADDRESSES
0
SP AFTER
INTERRUPT STACKING
*
SP BEFORE
THE INTERRUPT
TOWARD HIGHER ADDRESSES
Chapter 4 Interrupt
55
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