Table of Contents
Advertisement
Functional description
26.3.2.1 Alignment and compare output polarity
The edge-align (EDG) bit in the configure (CNFG) register selects either center-aligned
or edge-aligned PWM generator outputs.
PWM compare output polarity is selected by the CINVn bit field in the compare invert
(CINV) register. Please see the output operations in the following two figures.
The PWM compare output is driven to high state when the value of PWM value
(VAL0-5) register is greater than the value of PWM counter, and PWM compare is
counting downwards if the corresponding channel CINVx=0. Or, the PWM compare
output is driven to low state if the corresponding channel CINVx=1.
The PWM compare output is driven to low state when the value of PWM value
(VAL0-5) register matches the value of PWM counter, and PWM counter is counting
upwards if the corresponding channel CINVx=0. Or, the PWM compare output is driven
to high state if the corresponding channel CINVx=1.
Alignment Reference
Up/Down Counter
Modulus = 4
PWM Compare Output
Duty Cycle = 50%
Alignment Reference
Up Counter
Modulus = 4
PWM Compare Output
Duty Cycle = 50%
Because of the equals-comparator architecture of this PWM, the
modulus=0 case is considered illegal. However, the deadtime
constraints and fault conditions will still be guaranteed.
486
Figure 26-3. Center-Aligned PWM output
Figure 26-4. Edge-Aligned PWM output
NOTE
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
CINVx= 0
CINVx = 1
CINVx = 0
CINVx = 1
NXP Semiconductors
Advertisement
Table of Contents
