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Memory Map and Register Descriptions
Field
CMOD7_0
Counter Modulo 7:0
26.4.12 PWM Counter Register: High (PWM_CMODH)
The 15-bit unsigned value written to this buffered, read/write register defines the PWM
period in PWM clock periods. Reserved bit 15 cannot be modified. It is read as zero.
The PWM counter modulo register is buffered. The value
written does not take effect until the LDOK bit is set and the
next PWM load cycle begins. Reading CMOD reads the value
in a buffer. It is not necessarily the value the PWM generator is
currently using.
Address: 40h base + Bh offset = 4Bh
Bit
7
Read
0
Write
Reset
0
Field
7
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
CMOD14_8
Counter Modulo 14:8
26.4.13 PWM Value Register: Low (PWM_VALnL)
The 16-bit signed value in these buffered, read/write registers defines the PWM pulse
width in PWM clock periods for each PWM output channel.
The PWM value registers are buffered. The value written does
not take effect until the LDOK bit is set and the next PWM load
cycle begins. Reading VALn reads the value in a buffer and not
necessarily the value the PWM generator is currently using.
A PWM value less than or equal to zero deactivates the PWM output for the entire PWM
period. A PWM value greater than, or equal to the modulus, activates the PWM output
for the entire PWM period.
516
PWM_CMODL field descriptions
NOTE
6
5
0
0
PWM_CMODH field descriptions
NOTE
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
4
3
CMOD14_8
0
0
Description
2
1
0
0
NXP Semiconductors
0
0
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