Phcmp2 Filter Period Register (Gdu_Phcmp2Fpr) - NXP Semiconductors MC9S08SU16 Reference Manual

Memory map and register definition

25.6.11 PHCMP2 Filter Period Register (GDU_PHCMP2FPR)

Address: 20h base + Ah offset = 2Ah
Bit 7
Read
Write
Reset 0
Field
FILT_PER Filter Sample Period
When CR1[SE] is equal to zero, this field specifies the sampling period, in bus clock cycles, of the
comparator output filter. Setting FILT_PER to 0x0 disables the filter. Filter programming and latency
details appear in the Functional Description.
This field has no effect when CR1[SE] is equal to one. In that case, the external SAMPLE signal is used to
determine the sampling period.
25.6.12 PHCMP2 Status and Control Register (GDU_PHCMP2SCR)
Address: 20h base + Bh offset = 2Bh
Bit 7
Read 0
Write
Reset
0
Field
7–6 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
5 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
4 Comparator Interrupt Enable Rising
IER
The IER bit enables the CFR interrupt from the CMP. When this bit is set, an interrupt will be asserted
when the CFR bit is set.
0 Interrupt disabled.
1 Interrupt enabled.
3 Comparator Interrupt Enable Falling
IEF
The IEF bit enables the CFF interrupt from the CMP. When this bit is set, an interrupt will be asserted
when the CFF bit is set.
448
6 5
0 0
GDU_PHCMP2FPR field descriptions
6 5
0
IER
0 0
GDU_PHCMP2SCR field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
4 3
FILT_PER
0 0
Description
4 3
CFR
IEF
w1c
0 0
Description
2 1
0 0
2 1
CFF COUT
w1c
0 0
NXP Semiconductors
0
0
0
0