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Functional description
• A write to ADC_SC1 or a set of write to ADC_SC1 in FIFO mode (with ADCH bits
not all 1s) if software triggered operation is selected.
• A hardware trigger (ADHWT) event if hardware triggered operation is selected.
• The transfer of the result to the data registers when continuous conversion is enabled.
If continuous conversions are enabled, a new conversion is automatically initiated after
the completion of the current conversion. In software triggered operation, continuous
conversions begin after ADC_SC1 is written and continue until aborted. In hardware
triggered operation, continuous conversions begin after a hardware trigger event and
continue until aborted.
17.5.3.2 Completing conversions
A conversion is completed when the result of the conversion is transferred into the data
result register, ADC_R. This is indicated by the setting of ADC_SC1[COCO]. An
interrupt is generated if ADC_SC1[AIEN] is high at the time that ADC_SC1[COCO] is
set.
17.5.3.3 Aborting conversions
Any conversion in progress is aborted in the following cases:
• A write to ADC_SC1 occurs.
• The current conversion will be aborted and a new conversion will be initiated, if
ADC_SC1[ADCH] are not all 1s and ADC_SC4[AFDEP] are all 0s.
• The current conversion and the rest of conversions will be aborted and no new
conversion will be initialed, if ADC_SC4[AFDEP] are not all 0s.
• A new conversion will be initiated when the FIFO is re-fulfilled upon the levels
indicated by the ADC_SC4[AFDEP] bits).
• A write to ADC_SC2, ADC_SC3, ADC_SC4, ADC_CV occurs. This indicates a
mode of operation change has occurred and the current and rest of conversions (when
ADC_SC4[AFDEP] are not all 0s) are therefore invalid.
• The MCU is reset.
• The MCU enters Stop mode with ADACK not enabled.
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MC9S08SU16 Reference Manual, Rev. 5, 4/2017
NXP Semiconductors
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