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Chapter 18
Chip-specific ACMP information
Chip-specific ACMP information
18.1 CMP configuration information
The CMP features eight different inputs muxed with both positive and negative inputs to
the CMP. One is fixed connected to built-in 6-bit DAC output. Other inputs are internally
and externally mapped on GDU outputs and pinouts. Built-in 6-bit DAC output to GDU
as possible the reference of GDU phase detection comparator. The following table shows
the connection of CMP input assignments.
The CMP continues to operate in wait and stop modes if enabled and its interrupt can
wake the MCU.
Customization:
• Primary clock: BUSCLK (20 MHz)
• Alternate clock: None
• ACMP supply uses VDDX and VSS
• 6-bit DAC reference are Vin1 to VREFH (a PMC high accuracy reference) and Vin2
to VDDX
• The following table summarizes the signal connection of CMP module.
Module
CMP
NXP Semiconductors
Table 18-1. CMP module signals
Connection
CH0
CH1
CH2
CH3
6-bit DAC
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Signal
Connect to
PTA0/CMP0
PTA1/CMP1
PTA2/CMP2
6-bit DAC
To GDU
289
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