Functional Description - NXP Semiconductors MC9S08SU16 Reference Manual

Functional description

Field
PWTL PWT counter[7:0]
Low byte of PWT counter register.
20.5 Functional description
20.5.1 PWT counter and PWT clock pre-scaler
The pulse width timer (PWT) measures duration of a pulse or the period of a signal input
to the PWTIN by a 16-bit free running counter (PWT_CNTH:L). There is a clock pre-
scaler (CLKPRE) in PWT module that provides the frequency divided clock to the
PWT_CNTH:L.. The clock pre-scaler can select clock input from bus clock and
alternative clock by PWT_CR[PCLKS].
The PWT counter uses the frequency divided clock from CLKPRE for counter
advancing. The frequency of pre-scaler is programmable as the clock frequency divided
by 1, 2, 4, 8, 16, 32, 64, 128 (depending on the setting of PRE[2:0]).
When PWT_CNT is running, any edge to be measured after the trigger edge causes the
value of the PWT_CNT to be uploaded to the appropriate pulse width registers. At the
same time, PWT_CNT will be reset to $0000 and the clock pre-scaler output will also be
reset together. PWT_CNT will then start advancing again with the input clock. If the
PWTxCNT runs from 0xFFFF to 0x0000, the PWTOV bit is set.
20.5.2 Edge detection and capture control
The edge detection and capture control part detects measurement trigger edges and
controls when and which pulse width register(s) will be updated.
The edge detection logic determines from which edge appeared on PWTIN the pulse
width starts to be measured, when and which pulse width registers should be updated.
The PWTIN can be selected from one of four sources by configuring PINSEL[1:0].
As soon as the PWT is enabled, the 16-bit free counter will begin to count up until a edge
transistion on the selected PWTIN. Determined by PWT_CS[FCTLE] and PWTIN state,
the counter contents can be uploaded to the corresponding registers.
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PWTx_CNTL field descriptions
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
NXP Semiconductors