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Chapter 25
Gate Drive Unit (GDU)
25.1 Chip specific GDU information
This device has one GDU
The following table summarizes the signal connection of GDU module.
Predriver Phase U Top input
Predriver Phase U Bottom input
Predriver Phase V Top input
Predriver Phase V Bottom input
Predriver Phase W Top input
Predriver Phase W Bottom input
Limit ACMP0 output
Limit ACMP1 output
AMP0 analog output
AMP1 analog output
Phase detection ACMP0 output
Phase detection ACMP1 output
Phase detection ACMP2 output
Phase detection ACMP0 window input
Phase detection ACMP1 window input
Phase detection ACMP2 window input
25.2 Introduction
NXP Semiconductors
Table 25-1. GDU module signals connection
Signal
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Connect to
PWM0 (PWMA0)
PWM1 (PWMA1)
PWM2 (PWMB0)
PWM3 (PWMB1)
PWM4 (PWMC0)
PWM5 (PWMC1)
PWM_Fault2
PWM_Fault3
ADCA_AD5 and ADCB_AD5
ADCA_AD6 and ADCB_AD6
XB_IN12
XB_IN13
XB_IN14
XB_OUT10
XB_OUT11
XB_OUT12
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