Cmp Status And Control Register (Cmp_Scr) - NXP Semiconductors MC9S08SU16 Reference Manual

Memory Map/Register Definitions
Field
FILT_PER Filter Sample Period
When CR1[SE] is equal to zero, this field specifies the sampling period, in bus clock cycles, of the
comparator output filter. Setting FILT_PER to 0x0 disables the filter. Filter programming and latency
details appear in the Functional Description.
This field has no effect when CR1[SE] is equal to one. In that case, the external SAMPLE signal is used to
determine the sampling period.

18.10.4 CMP Status and Control Register (CMP_SCR)

Address: 68h base + 3h offset = 6Bh
Bit 7
Read 0
Write
Reset 0
Field
7–6 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
5 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
4 Comparator Interrupt Enable Rising
IER
The IER bit enables the CFR interrupt from the CMP. When this bit is set, an interrupt will be asserted
when the CFR bit is set.
0 Interrupt disabled.
1 Interrupt enabled.
3 Comparator Interrupt Enable Falling
IEF
The IEF bit enables the CFF interrupt from the CMP. When this bit is set, an interrupt will be asserted
when the CFF bit is set.
0 Interrupt disabled.
1 Interrupt enabled.
2 Analog Comparator Flag Rising
CFR
During normal operation, the CFR bit is set when a rising edge on COUT has been detected. In STOP
mode, CFR is level sensitive and as long as COUT is high CFR will be set. The CFR bit is cleared by
writing a logic one to the bit.
0 Rising edge on COUT has not been detected.
1 Rising edge on COUT has occurred.
1 Analog Comparator Flag Falling
CFF
298
CMP_FPR field descriptions
6 5
0
IER
0 0
CMP_SCR field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
4 3
CFR
IEF
w1c
0 0
Description
2 1
CFF COUT
w1c
0 0
NXP Semiconductors
0
0