Channel Status And Control (Ftmx_Cnsc) - NXP Semiconductors MC9S08SU16 Reference Manual

Memory map and register definition

19.4.8 Channel Status and Control (FTMx_CnSC)

CnSC contains the channel-interrupt-status flag and control bits used to configure the
interrupt enable, channel configuration, and pin function.
CPWMS
X
0
1
Address: 70h base + 5h offset + (3d × i), where i=0d to 1d
Bit 7
Read CHF
Write 0
Reset 0
Field
7 Channel Flag
CHF
Set by hardware when an event occurs on the channel. CHF is cleared by reading the CnSC register while
CHnF is set and then writing a 0 to the CHF bit. Writing a 1 to CHF has no effect.
If another event occurs between the read and write operations, the write operation has no effect; therefore,
CHF remains set indicating an event has occurred. In this case a CHF interrupt request is not lost due to
the clearing sequence for a previous CHF.
326
Table 19-3. Mode, edge, and level selection
MSnB:MSnA ELSnB:ELSnA
XX
00
01
1X
XX
6 5
CHIE MSB
0 0
FTMx_CnSC field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Mode
00 None
01 Input capture
10
11
01 Output compare
10
11
10 Edge-aligned PWM
X1
10 Center-aligned PWM
X1
4 3
MSA ELSB ELSA
0 0
Description
Configuration
Pin not used for FTM
Capture on Rising Edge
Only
Capture on Falling
Edge Only
Capture on Rising or
Falling Edge
Toggle Output on
match
Clear Output on match
Set Output on match
High-true pulses (clear
Output on match)
Low-true pulses (set
Output on match)
High-true pulses (clear
Output on match-up)
Low-true pulses (set
Output on match-up)
2 1
0
0 0
NXP Semiconductors
0
0
0