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Section number
27.1.1
Forcing active background.............................................................................................................................529
27.1.2
Features.......................................................................................................................................................... 529
27.2
Background debug controller (BDC)............................................................................................................................530
27.2.1
BKGD pin description................................................................................................................................... 531
27.2.2
Communication details.................................................................................................................................. 532
27.2.3
BDC commands............................................................................................................................................. 534
27.2.4
BDC hardware breakpoint............................................................................................................................. 537
27.3
On-chip debug system (DBG)...................................................................................................................................... 537
27.3.1
Comparators A and B.....................................................................................................................................538
27.3.2
Bus capture information and FIFO operation................................................................................................ 538
27.3.3
Change-of-flow information.......................................................................................................................... 539
27.3.4
Tag vs. force breakpoints and triggers........................................................................................................... 540
27.3.5
Trigger modes................................................................................................................................................ 541
27.3.6
Hardware breakpoints.................................................................................................................................... 542
27.4
Memory map and register description.......................................................................................................................... 543
27.4.1
BDC Status and Control Register (BDC_SCR)............................................................................................. 543
27.4.2
BDC Breakpoint Match Register: High (BDC_BKPTH).............................................................................. 545
27.4.3
BDC Breakpoint Register: Low (BDC_BKPTL).......................................................................................... 546
27.4.4
System Background Debug Force Reset Register (BDC_SBDFR)...............................................................546
28.1
Introduction...................................................................................................................................................................549
28.1.1
Features.......................................................................................................................................................... 549
28.1.2
Modes of operation........................................................................................................................................ 550
28.1.3
Block diagram................................................................................................................................................ 550
28.2
Signal description..........................................................................................................................................................551
28.3
Memory map and registers............................................................................................................................................551
28.3.1
Debug Comparator A High Register (DBG_CAH)....................................................................................... 552
28.3.2
Debug Comparator A Low Register (DBG_CAL)........................................................................................ 553
30
Title
Chapter 28
Debug module (DBG)
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Page
NXP Semiconductors
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