Resets - NXP Semiconductors MC9S08SU16 Reference Manual

have the ability to generate the not acknowledge after the transfer of each byte and before
the completion of the transaction. This requirement is important because SMBus does not
provide any other resend signaling. This difference in the use of the NACK signaling has
implications on the specific implementation of the SMBus port, especially in devices that
handle critical system data such as the SMBus host and the SBS components.
In the last byte of master receive slave transmit mode, the
master must send a NACK to the bus, so FACK must be
switched off before the last byte transmits.

21.5.5 Resets

The I2C module is disabled after a reset. The I2C module cannot cause a core reset.
21.5.6 Interrupts
The I2C module generates an interrupt when any of the events in the table found here
occur, provided that the IICIE bit is set.
The interrupt is driven by the IICIF bit (of the I2C Status Register) and masked with the
IICIE bit (of the I2C Control Register 1). The IICIF bit must be cleared (by software) by
writing 1 to it in the interrupt routine. The SMBus timeouts interrupt is driven by SLTF
and masked with the IICIE bit. The SLTF bit must be cleared by software by writing 1 to
it in the interrupt routine. You can determine the interrupt type by reading the Status
Register.
In master receive mode, the FACK bit must be set to zero
before the last byte transfer.
Interrupt source
Complete 1-byte transfer
Match of received calling address
Arbitration lost
2
I C bus stop detection
2
I C bus start detection
SMBus SCL low timeout
SMBus SCL high SDA low timeout
Wakeup from stop3 or wait mode
NXP Semiconductors
NOTE
NOTE
Table 21-6. Interrupt summary
STOPF
STARTF
SHTF2
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 21 Inter-Integrated Circuit (I2C)
Status Flag
TCF IICIF
IAAS IICIF
ARBL IICIF
IICIF
IICIF
SLTF IICIF
IICIF
IAAS IICIF
Local enable
IICIE
IICIE
IICIE
IICIE & SSIE
IICIE & SSIE
IICIE
IICIE & SHTF2IE
IICIE & WUEN
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