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5.5
Peripheral clock gating................................................................................................................................................. 68
6.1
Introduction...................................................................................................................................................................71
6.2
Features......................................................................................................................................................................... 71
6.2.1
Run mode....................................................................................................................................................... 71
6.2.2
Wait mode...................................................................................................................................................... 72
6.2.3
Stop mode...................................................................................................................................................... 72
6.2.4
Active BDM enabled in stop mode................................................................................................................72
6.2.5
Power modes behaviors................................................................................................................................. 73
6.3
Bandgap reference........................................................................................................................................................ 74
7.1
Introduction...................................................................................................................................................................75
7.2
Port control and interrupt module features................................................................................................................... 75
7.3
Signal multiplexing constraints.................................................................................................................................... 75
7.4
Pinout............................................................................................................................................................................ 76
7.4.1
Signal multiplexing and pin assignments.......................................................................................................76
7.4.2
Signal description table.................................................................................................................................. 77
7.4.3
Pinout ............................................................................................................................................................ 81
8.1
Introduction...................................................................................................................................................................83
8.2
Port data and data direction...........................................................................................................................................84
8.3
Internal pullup/pulldown enable................................................................................................................................... 84
8.4
Input glitch filter........................................................................................................................................................... 85
8.5
Memory map and register definition.............................................................................................................................86
8.5.1
Port A Data Register (PORT_PTAD)............................................................................................................ 86
8.5.2
Port B Data Register (PORT_PTBD)............................................................................................................ 87
8.5.3
Port C Data Register (PORT_PTCD)............................................................................................................ 87
NXP Semiconductors
Chapter 6
Chapter 7
Chapter 8
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
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