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Chapter 18 Chip-specific ACMP information
1. T
represents the intrinsic delay of the analog component plus the polarity select logic. T
is the clock period of the
PD
SAMPLE
external sample clock. T
is the period of the bus clock.
per
18.12 CMP Interrupts
The CMP module is capable of generating an interrupt on either the rising or falling edge
of the comparator output (or both). The interrupt request is asserted when both SCR[IER]
bit and SCR[CFR] are set. It is also asserted when both SCR[IEF] bit and SCR[CFF] are
set. The interrupt is de-asserted by clearing either SCR[IER] or SCR[CFR] for a rising
edge interrupt, or SCR[IEF] and SCR[CFF] for a falling edge interrupt.
18.13 Digital to Analog Converter Block Diagram
The following figure shows the block diagram of the DAC module. It contains a 64-tap
resistor ladder network and a 64-to-1 multiplexer, which selects an output voltage from
one of 64 distinct levels that outputs from DACO. It is controlled through DAC Control
register (DACCR). Its supply reference source can be selected from two sources V
and
in1
V
. The module can be powered down (disabled) when it is not used. When in disable
in2
mode, DACO is connected to the analog ground.
V
V
in1
in2
VOSEL[5:0]
DACEN
MUX
VRSEL
Vin
DACO
Figure 18-12. 6-bit DAC Block Diagram
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
NXP Semiconductors
315
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