Table of Contents
Advertisement
SMBus defines a clock low timeout, T
cumulative clock low extend time for a slave device, and specifies T
cumulative clock low extend time for a master device.
21.5.4.1.1 SCL low timeout
If the SCL line is held low by a slave device on the bus, no further communication is
possible. Furthermore, the master cannot force the SCL line high to correct the error
condition. To solve this problem, the SMBus protocol specifies that devices participating
in a transfer must detect any clock cycle held low longer than a timeout value condition.
Devices that have detected the timeout condition must reset the communication. When
the I2C module is an active master, if it detects that SMBCLK low has exceeded the
value of T
TIMEOUT,MIN
byte in the transfer process. When the I2C module is a slave, if it detects the
T
condition, it resets its communication and is then able to receive a new
TIMEOUT,MIN
START condition.
21.5.4.1.2 SCL high timeout
When the I2C module has determined that the SMBCLK and SMBDAT signals have
been high for at least T
A HIGH timeout occurs after a START condition appears on the bus but before a STOP
condition appears on the bus. Any master detecting this scenario can assume the bus is
free when either of the following occurs:
• SHTF1 rises.
• The BUSY bit is high and SHTF1 is high.
When the SMBDAT signal is low and the SMBCLK signal is high for a period of time,
another kind of timeout occurs. The time period must be defined in software. SHTF2 is
used as the flag when the time limit is reached. This flag is also an interrupt resource, so
it triggers IICIF.
21.5.4.1.3 CSMBCLK TIMEOUT MEXT and CSMBCLK TIMEOUT SEXT
The following figure illustrates the definition of the timeout intervals T
T
. When in master mode, the I2C module must not cumulatively extend its
LOW:MEXT
clock cycles for a period greater than T
defined as START-to-ACK, ACK-to-ACK, or ACK-to-STOP. When CSMBCLK
TIMEOUT MEXT occurs, SMBus MEXT rises and also triggers the SLTF.
NXP Semiconductors
TIMEOUT
, it must generate a stop condition within or after the current data
, it assumes that the bus is idle.
HIGH:MAX
LOW:MEXT
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 21 Inter-Integrated Circuit (I2C)
, of 35 ms, specifies T
within a byte, where each byte is
as the
LOW:SEXT
as the
LOW:MEXT
and
LOW:SEXT
385
Advertisement
Table of Contents
