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When the MCU is reset by SIM_SRS[ILAD], the address of illegal address is captured in
illegal address register, which is a 16-bit register consisting of SIM_ILLAL and
SIM_ILLAH that contains the LSB and MSB 8-bit of the address, respectively.
9.5 Computer operating properly (COP) watchdog
The COP watchdog is used to force a system reset when the application software fails to
execute as expected. To prevent a system reset from the COP timer (when it is enabled),
application software must reset the COP counter periodically. If the application program
gets lost and fails to reset the COP counter before it times out, a system reset is generated
to force the system back to an known starting point. After any reset, the COP watchdog is
enabled (see
System Options Register 1 (SIM_SOPT1)
COP watchdog is not used in an application, it can be disabled by clearing
SOPT1[COPT].
The COP counter is reset by writing 0x55 and 0xAA (in this order) to the address of SRS
during the selected timeout period. Writes do not affect the data in the read-only SRS. As
soon as the write sequence is done, the COP timeout period is restarted. If the program
fails to do this during the time-out period, the MCU will reset. Also, if any value other
than 0x55 or 0xAA is written to SRS, the MCU is immediately reset. The
SOPT1[COPCLKS] selects the clock source used for the COP timer. The clock source
options are
• bus clock;
• internal 20 kHz LPO clock source
• 32 kHz ICSIRCLK
• CLK_IN from external pin
With each clock source, there are three associated time-outs controlled by
SOPT1[COPT]. The following table summaries the control functions of the
SOPT1[COPCLKS] and SOPT1[COPT] bits. The COP watchdog defaults to operation
from the 20 kHz LPO clock source and the longest time-out (2
When the bus clock source is selected, windowed COP operation is available by setting
SOPT1[COPW]. In this mode, writes to the SRS register to clear the COP timer must
occur in the last 25% of the selected timeout period. A premature write immediately
resets the MCU. When the LPO, ICSIRCLK, or CLK_IN clock source is selected,
windowed COP operation is not available. The COP counter is initialized by the first
writes to the SOPT1 registers and after any system reset. Subsequent writes to SOPT1
have no effect on COP operation. Even if the application will use the reset default
settings of SOPT1[COPT], SOPT1[COPCLKS], and SOPT1[COPW] bits, the user must
write to the write-once SOPT1 register during reset initialization to lock in the settings.
NXP Semiconductors
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 9 System Integration Module (SIM)
for additional information). If the
10
cycles).
99
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