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Register definition
Absolute
address
(hex)
1868
SCI Baud Rate Register: High (SCI0_BDH)
1869
SCI Baud Rate Register: Low (SCI0_BDL)
186A
SCI Control Register 1 (SCI0_C1)
186B
SCI Control Register 2 (SCI0_C2)
186C
SCI Status Register 1 (SCI0_S1)
186D
SCI Status Register 2 (SCI0_S2)
186E
SCI Control Register 3 (SCI0_C3)
186F
SCI Data Register (SCI0_D)
22.4.1 SCI Baud Rate Register: High (SCIx_BDH)
This register, along with SCI_BDL, controls the prescale divisor for SCI baud rate
generation. To update the 13-bit baud rate setting [SBR12:SBR0], first write to
SCI_BDH to buffer the high half of the new value and then write to SCI_BDL. The
working value in SCI_BDH does not change until SCI_BDL is written.
Address: 1868h base + 0h offset = 1868h
Bit
7
Read
LBKDIE
Write
Reset
0
Field
7
LIN Break Detect Interrupt Enable (for LBKDIF)
LBKDIE
0
Hardware interrupts from SCI_S2[LBKDIF] disabled (use polling).
1
Hardware interrupt requested when SCI_S2[LBKDIF] flag is 1.
6
RxD Input Active Edge Interrupt Enable (for RXEDGIF)
RXEDGIE
0
Hardware interrupts from SCI_S2[RXEDGIF] disabled (use polling).
1
Hardware interrupt requested when SCI_S2[RXEDGIF] flag is 1.
5
Stop Bit Number Select
SBNS
SBNS determines whether data characters are one or two stop bits.
0
One stop bit.
1
Two stop bit.
SBR
Baud Rate Modulo Divisor.
400
SCI memory map
Register name
6
5
RXEDGIE
SBNS
0
0
SCIx_BDH field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Width
Access
(in bits)
8
R/W
8
R/W
8
R/W
8
R/W
8
8
R/W
8
R/W
8
R/W
4
3
SBR
0
0
Description
Section/
Reset value
page
00h
22.4.1/400
04h
22.4.2/401
00h
22.4.3/401
00h
22.4.4/403
R
C0h
22.4.5/404
00h
22.4.6/406
00h
22.4.7/407
00h
22.4.8/409
2
1
0
0
NXP Semiconductors
0
0
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