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Memory map and registers
Field
7
DBG Module Enable Bit
DBGEN
The DBGEN bit enables the DBG module. The DBGEN bit is forced to zero and cannot be set if the MCU
is secure.
0
DBG not enabled.
1
DBG enabled.
6
Arm Bit
ARM
The ARM bit controls whether the debugger is comparing and storing data in FIFO.
0
Debugger not armed.
1
Debugger armed.
5
Tag or Force Bit
TAG
The TAG bit controls whether a debugger or comparator C breakpoint will be requested as a tag or force
breakpoint to the CPU. The TAG bit is not used if BRKEN = 0.
0
Force request selected.
1
Tag request selected.
4
Break Enable Bit
BRKEN
The BRKEN bit controls whether the debugger will request a breakpoint to the CPU at the end of a trace
run, and whether comparator C will request a breakpoint to the CPU.
0
CPU break request not enabled.
1
CPU break request enabled.
3–1
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
0
Select LOOP1 Capture Mode
LOOP1
This bit selects either normal capture mode or LOOP1 capture mode. LOOP1 is not used in event-only
modes.
0
Normal operation - capture COF events into the capture buffer FIFO.
1
LOOP1 capture mode enabled. When the conditions are met to store a COF value into the FIFO,
compare the current COF address with the address in comparator C. If these addresses match,
override the FIFO capture and do not increment the FIFO count. If the address does not match
comparator C, capture the COF address, including the PPACC indicator, into the FIFO and into
comparator C..
28.3.14 Debug Trigger Register (DBG_T)
The figure shows the values in POR or non-end-run reset. All
the bits are undefined in end-run reset. In the case of an end-
trace to reset where DBGEN=1 and BEGIN=0, the ARM and
BRKEN bits are cleared but the remaining control bits in this
register do not change after reset.
562
DBG_C field descriptions
NOTE
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
NXP Semiconductors
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