Phcmp1 Filter Period Register (Gdu_Phcmp1Fpr) - NXP Semiconductors MC9S08SU16 Reference Manual

Memory map and register definition
Field
This bit allows you to select the polarity of the GDU analog comparator function. It is also driven to the
COUT output (on both the device pin and as SCR[COUT]) when CR1[OPE]=0.
0 Does not invert the GDU comparator output.
1 Inverts the GDU comparator output.
2 Comparator Output Select
COS
NOTE: This field is always disabled in this device, writing 1 to this field does not take effect.
0 Set CMPO to equal COUT (filtered comparator output).
1 Set CMPO to equal COUTA (unfiltered comparator output).
1 Comparator Output Pin Enable
OPE
NOTE: This field is always disabled in this device, writing 1 to this field does not take effect.
0 The comparator output (CMPO) is not available on the associated CMPO output pin.
1
The comparator output (CMPO) is available on the associated CMPO output pin.
0 Comparator Module Enable
EN
The EN bit enables the Analog Comparator Module. When the module is not enabled, it remains in the off
state, and consumes no power. When you select the same input from analog mux to the positive and
negative port, the comparator is disabled automatically.
0 Analog Comparator disabled.
1 Analog Comparator enabled.

25.6.7 PHCMP1 Filter Period Register (GDU_PHCMP1FPR)

Address: 20h base + 6h offset = 26h
Bit 7
Read
Write
Reset 0
Field
FILT_PER Filter Sample Period
When CR1[SE] is equal to zero, this field specifies the sampling period, in bus clock cycles, of the
comparator output filter. Setting FILT_PER to 0x0 disables the filter. Filter programming and latency
details appear in the Functional Description.
This field has no effect when CR1[SE] is equal to one. In that case, the external SAMPLE signal is used to
determine the sampling period.
444
GDU_PHCMP1CR1 field descriptions (continued)
6 5
0 0
GDU_PHCMP1FPR field descriptions
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
4 3
FILT_PER
0 0
Description
2 1
0 0
NXP Semiconductors
0
0