Initializing Fee Mode; Initializing Fbe Mode - NXP Semiconductors MC9S08SU16 Reference Manual

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Chapter 12 Internal Clock Source (ICS)
/* the following code segment demonstrates setting the ICS to FBI mode using the factory
trim value. The resulting ICSOUT frequency is fint_ft/BDIV. Note that the FLL will be
running at a frequency of fint_ft*1024/BDIV even though the FLL is bypassed. */
ICS_C2 = 0x20; // BDIV=divide by 2 – use default until clock dividers configured
ICS_C1 = 0x44; // internal reference clock as source for ICSOUT
while ((ICS_S & 0x0C) != 0x04); // wait until internal reference is selected
ICS_C2 = 0x00; // BDIV=divide by 1 – allows max core and bus clock frequencies

12.5.3 Initializing FEE mode

The following code segment demonstrates setting ICS to FEE mode.
Example: 12.5.3.1 FEE mode initialization routine
/* the following code segment demonstrates setting the ICS to FEE mode generating a 32MHZ
bus clock frequency using an external 8MHz crystal */
SIM_SOPT1[RANGE] = 1; // high range
ICS_C2 = 0x20; // BDIV=divide by 2 – use default until clock dividers configured
ICS_C1 = 0x18; // 8MHz external reference clock/256 as source to FLL
while ((ICS_S & ICS_S_IREFST_MASK) == 1); // wait for external source selected
while ((ICS_S & ICS_S_LOCK_MASK) == 0); // wait for FLL to lock
ICS_C2 = 0x00; // BDIV=divide by 1 – allows max core and bus clock frequencies

12.5.4 Initializing FBE mode

The following code segment demonstrates setting ICS to FBE mode.
Example: 12.5.4.1 FBE mode initialization routine
/* the following code segment demonstrates setting the ICS to FBE mode generating 20MHZ core
clock frequency using an external 20MHz crystal */
SIM_SOPT1[RANGE] = 1; // high range
ICS_C2 = 0x20; // BDIV=divide by 2 – use default until clock dividers configured
ICS_C1 = 0xA0; // 20MHz external clock as ICSOUT source; FLL source = 20MHz/512
while ((ICS_S & ICS_S_IREFST_MASK) == 1); // wait for external source selected
while ((ICS_S & 0x0C) != 0x08); // wait until FBE mode is selected
ICS_C2 = 0x00; // BDIV=divide by 1 – allows max core and bus clock frequencies
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
NXP Semiconductors
203

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