Mtim16 Counter Register Low (Mtim_Cntl) - NXP Semiconductors MC9S08SU16 Reference Manual

Memory Map and Register Descriptions
Address: 8h base + 2h offset = Ah
Bit 7
Read
Write
Reset 0
Field
CNTH MTIM16 count (high byte)
These 8 read-only bits contain the current high byte value of the 16-bit counter. Writing has no effect on
this register. Reset clears the register to 0x00.

13.5.4 MTIM16 counter register low (MTIM_CNTL)

This register is the read-only value of the low byte of the current MTIM16 16-bit counter.
When either the CNTH or CNTL register is read, the content of the two registers is
latched into a buffer where they remain latched until the other register is read. This
allows the coherent 16-bit value to be read in both big-endian and little-endian compile
environments and ensures the 16-bit counter is unaffected by the read operation. The
coherency mechanism is automatically restarted by an MCU reset or by setting the TRST
bit of the SC register (whether BDM mode is active or not).
When BDM is active, the coherency mechanism is frozen such that the buffer latches
remain in the state they were in when BDM became active, even if one or both halves of
the counter register are read while BDM is active. This assures that if the user was in the
middle of reading a 16-bit register when BDM became active, the appropriate value from
the other half of the 16-bit value is read after returning to normal execution. The value
read from the CNTH and CNTL registers in BDM mode is the value of these registers
and not the value of their read buffer.
Address: 8h base + 3h offset = Bh
Bit 7
Read
Write
Reset 0
Field
CNTL MTIM16 count (low byte)
212
6 5
0 0
MTIM_CNTH field descriptions
6 5
0 0
MTIM_CNTL field descriptions
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
4 3
CNTH
0 0
Description
4 3
CNTL
0 0
Description
2 1
0 0
2 1
0 0
NXP Semiconductors
0
0
0
0