NXP Semiconductors MC9S12G Reference Manual

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MC9S12G Family

Reference Manual

and Data Sheet

S12

Microcontrollers

MC9S12GRMV1

Rev.1.27

October 23, 2017

nxp.com

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Page 1 MC9S12G Family Reference Manual and Data Sheet Microcontrollers MC9S12GRMV1 Rev.1.27 October 23, 2017 nxp.com...
Page 2 Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: nxp.com/ A full list of family members and options is included in the appendices. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 3 Chapter 17, “Digital Analog Converter (DAC_8B5V)” (Reason: Spec update) Aug, 2014 1.25 • Fixed issues with hidden text throughout the document • Updated Chapter 1, “Device Overview MC9S12G-Family Jun, 2017 1.26 (added mask set information to Table 1-5) • Updated Appendix A, “Electrical Characteristics...
Page 4 This document contains information for all constituent modules, with the exception of the CPU. For CPU information please refer to CPU12-1 in the CPU12 & CPU12X Reference Manual MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 5 Chapter 1 Device Overview MC9S12G-Family ......29 Chapter 2 Port Integration Module (S12GPIMV1) ......149 Chapter 3 5V Analog Comparator (ACMPV1) .
Page 6 Package and Die Information ....... . . 1255 MC9S12G Family Reference Manual Rev.1.27...
Page 7: Table Of Contents
1.2.1 MC9S12G-Family Comparison ........
Page 8 2.4.3 Register Descriptions ........... 196 MC9S12G Family Reference Manual Rev.1.27...
Page 9 5.1.5 Block Diagram ............260 MC9S12G Family Reference Manual Rev.1.27...
Page 10 7.4.1 Security ............. 288 MC9S12G Family Reference Manual Rev.1.27...
Page 11 8.5.11 Scenario 10 ............344 MC9S12G Family Reference Manual Rev.1.27...
Page 12 10.6.1 Description of Interrupt Operation ........398 MC9S12G Family Reference Manual Rev.1.27...
Page 13 13.1.3 Block Diagram ............458 MC9S12G Family Reference Manual Rev.1.27...
Page 14 15.6 Interrupts ..............531 MC9S12G Family Reference Manual Rev.1.27...
Page 15 18.1 Introduction ..............569 MC9S12G Family Reference Manual Rev.1.27...
Page 16 20.1 Introduction ..............653 MC9S12G Family Reference Manual Rev.1.27...
Page 17 21.4.3 Transmission Formats ..........706 MC9S12G Family Reference Manual Rev.1.27...
Page 18 23.4.6 Gated Time Accumulation Mode ......... . 762 MC9S12G Family Reference Manual Rev.1.27...
Page 19 25.4 Functional Description ............839 MC9S12G Family Reference Manual Rev.1.27...
Page 20 27.1 Introduction ..............917 MC9S12G Family Reference Manual Rev.1.27...
Page 21 28.5.1 Unsecuring the MCU using Backdoor Key Access ......1017 MC9S12G Family Reference Manual Rev.1.27...
Page 22 30.4.3 Internal NVM resource (NVMRES) ........1100 MC9S12G Family Reference Manual Rev.1.27...
Page 23 A.1.3 Pins ..............1179 MC9S12G Family Reference Manual Rev.1.27...
Page 24 D.2 64 LQFP Mechanical Dimensions ..........1259 MC9S12G Family Reference Manual Rev.1.27...
Page 25 D.7 KGD Information ............1273 MC9S12G Family Reference Manual Rev.1.27...
Page 26 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 27: Chapter 1 Device Overview Mc9S12G-Family
RKE receivers, smart actuators, lighting modules, and smart junction boxes. The MC9S12G-Family uses many of the same features found on the MC9S12XS- and MC9S12P-Family, including error correction code (ECC) on flash memory, a fast analog-to-digital converter (ADC) and a frequency modulated phase locked loop (IPLL) that improves the EMC performance.
Page 28: Features
Device Overview MC9S12G-Family The MC9S12G-Family is optimized for lower program memory sizes down to 16k. In order to simplify customer use it features an EEPROM with a small 4 bytes erase sector size. The MC9S12G-Family deliver all the advantages and efficiencies of a 16-bit MCU while retaining the low cost, power consumption, EMC, and code-size efficiency advantages currently enjoyed by users of NXP’s...
Page 29 6 = 0 … 5 8 = 0 … 7 8 = 0 … 7 12 = 0 … 11 16 = 0 … 15 16 = 0 … 15 16 = 0 … 15 MC9S12G Family Reference Manual Rev.1.27...
Page 30: Chip-Level Features
Precision fixed voltage reference for ADC conversions • Optional reference voltage attenuator module to increase ADC accuracy Module Features The following sections provide more details of the modules implemented on the MC9S12G-Family family. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 31: S12 16-Bit Central Processor Unit (Cpu)
— Automatic index predecrement, preincrement, postdecrement, and postincrement (by –8 to +8) 1.3.2 On-Chip Flash with ECC On-chip flash memory on the MC9S12G-Family family features the following: • Up to 240 Kbyte of program flash memory — 32 data bits plus 7 syndrome ECC (error correction code) bits allow single bit error correction and double fault detection —...
Page 32: Main External Oscillator (Xosclcp)
— Automatic frequency lock detector — Configurable option to spread spectrum for reduced EMC radiation (frequency modulation) — Reference clock sources: – External 4–16 MHz resonator/crystal (XOSCLCP) – Internal 1 MHz RC oscillator (IRC) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 33: System Integrity Support
— 2 x 32-bit — 4 x 16-bit — 8 x 8-bit • Wakeup with integrated low pass filter option • Loop back for self test • Listen-only mode to monitor CAN bus MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 34: Serial Communication Interface Module (Sci)
— Multiple channel scans — Precision fixed voltage reference for ADC conversions — • Pins can also be used as digital I/O including wakeup capability 1. 12-bit resolution only available on S12GA192 and S12GA240 devices. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 35: Reference Voltage Attenuator (Rva)
Two types of comparator matches — Tagged This matches just before a specific instruction begins execution — Force This is valid on the first instruction boundary after a match occurs • Four trace modes MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 36: Key Performance Parameters
— 32-pin LQFP, 0.8 mm pitch, 7 mm x 7 mm outline — 20 TSSOP, 0.65 mm pitch, 4.4 mm x 6.5 mm outline — Known good die (KGD), unpackaged Block Diagram Figure 1-1 shows a block diagram of the MC9S12G-Family. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 37: Ps3
Not all pins or all peripherals are available on all devices and packages. Rerouting options are not shown. Figure 1-1. MC9S12G-Family Block Diagram Family Memory Map Table 1-3 shows the MC9S12G-Family register memory map. Table 1-3. Device Register Memory Map Size Address Module (Bytes) 0x0000–0x0009...
Page 38 ACMP (Analog Comparator) 0x0262–0x0275 PIM (Port Integration Module) 0x0276 RVA (Reference Voltage Attenuator) 0x0277–0x027F PIM (Port Integration Module) 0x0280–0x02EF Reserved 0x02F0–0x02FF CPMU (Clock and Power Management) 0x0300–0x03BF Reserved 0x03C0–0x03C7 DAC0 (Digital to Analog Converter) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 39 P-Flash, EEPROM and RAM. The whole 256K global memory space is visible through the P-Flash window located in the 64k local memory map located at 0x8000 - 0xBFFF using the PPAGE register. Table 1-4. MC9S12G-Family Memory Parameters S12G48 S12G192...
Page 40 Device Overview MC9S12G-Family Table 1-4. MC9S12G-Family Memory Parameters S12G48 S12G192 S12G240 Feature S12GN16 S12GN32 S12G64 S12G96 S12G128 S12GN48 S12GA192 S12GA240 RAM [Bytes] 1024 2048 4096 4096 8192 8192 11264 11264 RAM_LOW 0x3C00 0x3800 0x3000 0x3000 0x2000 0x2000 0x1400 0x1400 Unpaged Flash —...
Page 41 Flash Space Flash Space Page 0xD Page 0xD 0x3_8000 Flash Space Flash Space Page 0xE Page 0xE 0x3_C000 Flash Space Flash Space Page 0xF Page 0xF 0x3_FFFF Figure 1-2. MC9S12G Global Memory Map MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 42: Part Id Assignments
0xF280 0N75C 0xF280 0N55V 0xF280 MC9S12G48 1N75C 0xF281 1N55V 0xF281 0N75C 0xF280 0N55V 0xF280 MC9S12GN48 1N75C 0xF281 1N55V 0xF281 0N48A 0xF380 MC9S12GNA32 0N57V 0xF380 0N48A 0xF380 0N57V 0xF380 MC9S12GN32 1N48A 0xF381 1N57V 0xF381 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 43: Signal Description And Device Pinouts
100 LQFP KGD (Die) 48 QFN Port AD/ADC Channels Port A pins Port B pins Port C pins Port D pins Port E pins Port J Port M Port P Port S Port T MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 44: Detailed Signal Descriptions
PAD[15:0] / KWAD[15:0] — Port AD Input Pins of ADC PAD[15:0] are general-purpose input or output signals. These signals can have a pull-up or pull-down device selected and enabled on per signal basis. Out of reset the pull devices are disabled. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 45 PS[7:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected and enabled on per signal basis. Out of reset the pull-up devices are enabled. The signals can be configured on per pin basis in open-drain mode. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 46 These analog input pins areused as input signals for the operational amplifiers positive input pins when the according mode is selected. 1.7.2.18.4 AMPM[1:0] Input Pins These analog input pins are used as input signals for the operational amplifiers negative input pin when the according mode is selected. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 47 (MSCAN). 1.7.2.21.2 TXCAN Signal This signal is associated with the transmit functionality of the scalable controller area network controller (MSCAN). 1.7.2.22 PWM[7:0] Signals The signals PWM[7:0] are associated with the PWM module outputs. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 48: Power Supply Pins
1.7.3 Power Supply Pins MC9S12G power and ground pins are described below. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible.
Page 49 Refer to Section 1.18, “ADC VRH/VRL Signal Connection” for further details. On some packages VRH is tied to VDDA or VDDXRA. Refer to section Device Pinouts for further details. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 50 For the 20- and 32-pin package the VDDX, VDDR and VDDA supplies are combined on one pin. VSSXA Return ground for I/O driver and VDDA analog supply 3.15V – 5.0 V Reference voltage for the analog-to-digital converter. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 51: Device Pinouts
— — — — PERT/PPST Disabled PAD0 KWAD0 — — — — — PER1AD/PPS1AD Disabled PAD1 KWAD1 — — — — — PER1AD/PPS1AD Disabled PAD2 KWAD2 — — — — — PER1AD/PPS1AD Disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 52 Disabled ETRIG2 PWM2 RXD0 MISO0 — — — PERS/PPSS IOC2 MOSI0 — — — — — PERS/PPSS The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 53 Resistor Power Supply Reset Package Pin CTRL Func. Func. Func Func State RESET — — — — PULLUP VDDXRA — — — — — — VSSXA — — — — — — — MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 54: Ps4
— — PERS/PPSS TXD0 — — — PERS/PPSS PWM4 MISO0 — — PERS/PPSS IOC4 MOSI0 — — PERS/PPSS IOC5 SCK0 — — PERS/PPSS API_EXTCLK ECLK PWM5 PERS/PPSS — — — — PERM/PPSM Disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 55 VDDXR PAD5/KWAD5/AN5 VSSX S12GN16 PAD4/KWAD4/AN4 EXTAL/PE0 S12GN32 PAD11/KWAD11/ACMPM PAD3/KWAD3/AN3 XTAL/PE1 PAD10/KWAD10/ACMPP TEST 48-Pin LQFP/QFN PAD2/KWAD2/AN2 KWJ0/PJ0 PAD9/KWAD9/ACMPO KWJ1/PJ1 PAD1/KWAD1/AN1 KWJ2/PJ2 PAD8/KWAD8 KWJ3/PJ3 PAD0/KWAD0/AN0 BKGD Figure 1-5. 48-Pin LQFP/QFN Pinout for S12GN16 and S12GN32 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 56 — PERT/PPST Disabled IOC1 — — PERT/PPST Disabled IOC0 XIRQ — — PERT/PPST Disabled PAD0 KWAD0 — — PER1AD/PPS1AD Disabled PAD8 KWAD8 — — — PER0AD/PPS0AD Disabled PAD1 KWAD1 — — PER1AD/PPS1AD Disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 57 PERS/PPSS API_EXTC ECLK — PERS/PPSS — — — — PERM/PPSM Disabled — — — — PERM/PPSM Disabled The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 58: S12Gna16 And S12Gna32
Figure 1-6. 48-Pin LQFP/QFN Pinout for S12GNA16 and S12GNA32 Table 1-11. 48-Pin LQFP/QFN Pinout for S12GNA16 and S12GNA32 Function Internal Pull <----lowest-----PRIORITY-----highest----> Resistor Power Supply Reset Package Pin CTRL Func. Func. Func Func State RESET — — — — PULLUP MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 59 Disabled PAD0 KWAD0 — — PER1AD/PPS1AD Disabled PAD8 KWAD8 — — — PER0AD/PPS0AD Disabled PAD1 KWAD1 — — PER1AD/PPS1AD Disabled PAD9 KWAD9 ACMPO — — PER0AD/PPS0AD Disabled PAD2 KWAD2 — — PER1AD/PPS1AD Disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 60: S12Gn48
— — — PERM/PPSM Disabled — — — — PERM/PPSM Disabled The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled 1.8.3 S12GN48 1.8.3.1 Pinout 32-Pin LQFP MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 61 Func. Func. Func Func State RESET — — — — PULLUP VDDXRA — — — — — — VSSXA — — — — — — — EXTAL — — — — PUCR/PDPEE Down MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 62 — PERS/PPSS PWM4 MISO0 — — PERS/PPSS IOC4 MOSI0 — — PERS/PPSS IOC5 SCK0 — — PERS/PPSS API_EXTCLK ECLK PWM5 PERS/PPSS RXD1 — — — PERM/PPSM Disabled TXD1 — — — PERM/PPSM Disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 63 PAD7/KWAD7/AN7 RESET PAD6/KWAD6/AN6 VDDXR PAD5/KWAD5/AN5 VSSX S12GN48 PAD4/KWAD4/AN4 EXTAL/PE0 PAD11/KWAD11/AN11/ACMPM PAD3/KWAD3/AN3 XTAL/PE1 48-Pin LQFP PAD10/KWAD10/AN10/ACMPP TEST PAD2/KWAD2/AN2 MISO1/KWJ0/PJ0 PAD9/KWAD9/AN9/ACMPO MOSI1/KWJ1/PJ1 PAD1/KWAD1/AN1 SCK1/KWJ2/PJ2 PAD8/KWAD8/AN8 SS1/KWJ3/PJ3 PAD0/KWAD0/AN0 BKGD Figure 1-8. 48-Pin LQFP Pinout for S12GN48 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 64 — — PERT/PPST Disabled IOC1 — — PERT/PPST Disabled IOC0 XIRQ — — PERT/PPST Disabled PAD0 KWAD0 — — PER1AD/PPS1AD Disabled PAD8 KWAD8 — — PER0AD/PPS0AD Disabled PAD1 KWAD1 — — PER1AD/PPS1AD Disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 65 PERS/PPSS API_EXTC ECLK — PERS/PPSS — — — — PERM/PPSM Disabled — — — — PERM/PPSM Disabled The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 66 PAD13/KWAD13 VDDX VDDR PAD5/KWAD5/AN5 S12GN48 VSSX PAD12/KWAD12 EXTAL/PE0 PAD4/KWAD4/AN4 PAD11/KWAD11/AN11/ACMPM 64-Pin LQFP PAD3/KWAD3/AN3 XTAL/PE1 TEST PAD10/KWAD10/AN10/ACMPP MISO1/KWJ0/PJ0 PAD2/KWAD2/AN2 MOSI1/KWJ1/PJ1 PAD9/KWAD9/AN9/ACMPO SCK1/KWJ2/PJ2 PAD1/KWAD1/AN1 PAD8/KWAD8/AN8 SS1/KWJ3/PJ3 PAD0/KWAD0/AN0 BKGD Figure 1-9. 64-Pin LQFP Pinout for S12GN48 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 67 PWM5 — — PERP/PPSP Disabled KWP6 — — PERP/PPSP Disabled KWP7 — — PERP/PPSP Disabled — — — — PERT/PPST Disabled — — — — PERT/PPST Disabled IOC5 — — — PERT/PPST Disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 68 VSSA — — — — — — — RXD0 — — — PERS/PPSS TXD0 — — — PERS/PPSS RXD1 — — — PERS/PPSS TXD1 — — — PERS/PPSS MISO0 — — — PERS/PPSS MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 69: Pm2
— — — — PERM/PPSM Disabled — — — — PERM/PPSM Disabled KWJ7 — — — PERJ/PPSJ The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 70: S12G48 And S12G64
Figure 1-10. 32-Pin LQFP Pinout for S12G48 and S12G64 Table 1-15. 32-Pin LQFP Pinout for S12G48 and S12G64 Function Internal Pull <----lowest-----PRIORITY-----highest----> Resistor Power Supply Reset Package Pin CTRL Func. Func. Func Func State RESET — — — — PULLUP MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 71 PER1AD/PPS1AD Disabled PAD7 KWAD7 ACMPM — PER1AD/PPS1AD Disabled RXD0 — — — PERS/PPSS TXD0 — — — PERS/PPSS PWM4 MISO0 — — PERS/PPSS IOC4 MOSI0 — — PERS/PPSS IOC5 SCK0 — — PERS/PPSS MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 72 State API_EXTCLK ECLK PWM5 PERS/PPSS RXD1 RXCAN — — PERM/PPSM Disabled TXD1 TXCAN — — PERM/PPSM Disabled The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 73 Table 1-16. 48-Pin LQFP Pinout for S12G48 and S12G64 Function Internal Pull <----lowest-----PRIORITY-----highest----> Resistor Power Supply Reset Package Pin CTRL Func. Func. Func Func State RESET — — — — PULLUP VDDXR — — — — — — — MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 74 — PER1AD/PPS1AD Disabled PAD8 KWAD8 — — PER0AD/PPS0AD Disabled PAD1 KWAD1 — — PER1AD/PPS1AD Disabled PAD9 KWAD9 ACMPO — PER0AD/PPS0AD Disabled PAD2 KWAD2 — — PER1AD/PPS1AD Disabled PAD10 KWAD10 AN10 ACMPP PER0AD/PPS0AD Disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 75 PERS/PPSS API_EXTC ECLK — PERS/PPSS RXCAN — — — PERM/PPSM Disabled TXCAN — — — PERM/PPSM Disabled The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 76 PAD5/KWAD5/AN5 S12G48 VSSX PAD12/KWAD12 S12G64 EXTAL/PE0 PAD4/KWAD4/AN4 PAD11/KWAD11/AN11/ACMPM PAD3/KWAD3/AN3 XTAL/PE1 64-pin LQFP TEST PAD10/KWAD10/AN10/ACMPP MISO1/KWJ0/PJ0 PAD2/KWAD2/AN2 MOSI1/KWJ1/PJ1 PAD9/KWAD9/AN9/ACMPO SCK1/KWJ2/PJ2 PAD1/KWAD1/AN1 PAD8/KWAD8/AN8 SS1/KWJ3/PJ3 PAD0/KWAD0/AN0 BKGD Figure 1-12. 64-Pin LQFP Pinout for S12G48 and S12G64 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 77 — PERP/PPSP Disabled KWP6 — — — PERP/PPSP Disabled KWP7 — — — PERP/PPSP Disabled — — — — PERT/PPST Disabled — — — — PERT/PPST Disabled IOC5 — — — PERT/PPST Disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 78: Miso0
VSSA — — — — — — — RXD0 — — — PERS/PPSS TXD0 — — — PERS/PPSS RXD1 — — — PERS/PPSS TXD1 — — — PERS/PPSS MISO0 — — — PERS/PPSS MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 79: Mosi0
— — — — PERM/PPSM Disabled — — — — PERM/PPSM Disabled KWJ7 — — — PERJ/PPSJ The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 80: S12Ga48 And S12Ga64
Figure 1-13. 48-Pin LQFP Pinout for S12GA48 and S12GA64 Table 1-18. 48-Pin LQFP Pinout for S12GA48 and S12GA64 Function Internal Pull <----lowest-----PRIORITY-----highest----> Resistor Power Supply Reset Package Pin CTRL Func. Func. Func Func State RESET — — — — PULLUP MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 81 — PERT/PPST Disabled PAD0 KWAD0 — — PER1AD/PPS1AD Disabled PAD8 KWAD8 — — PER0AD/PPS0AD Disabled PAD1 KWAD1 — — PER1AD/PPS1AD Disabled PAD9 KWAD9 ACMPO — PER0AD/PPS0AD Disabled PAD2 KWAD2 — — PER1AD/PPS1AD Disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 82 PERS/PPSS API_EXTC ECLK — PERS/PPSS RXCAN — — — PERM/PPSM Disabled TXCAN — — — PERM/PPSM Disabled The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 83 PAD5/KWAD5/AN5 S12GA48 VSSX PAD12/KWAD12 S12GA64 EXTAL/PE0 PAD4/KWAD4/AN4 PAD11/KWAD11/AN11/ACMPM PAD3/KWAD3/AN3 XTAL/PE1 64-pin LQFP TEST PAD10/KWAD10/AN10/ACMPP MISO1/KWJ0/PJ0 PAD2/KWAD2/AN2 MOSI1/KWJ1/PJ1 PAD9/KWAD9/AN9/ACMPO SCK1/KWJ2/PJ2 PAD1/KWAD1/AN1 PAD8/KWAD8/AN8 SS1/KWJ3/PJ3 PAD0/KWAD0/AN0 BKGD Figure 1-14. 64-Pin LQFP Pinout for S12GA48 and S12GA64 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 84 — PERP/PPSP Disabled KWP6 — — — PERP/PPSP Disabled KWP7 — — — PERP/PPSP Disabled — — — — PERT/PPST Disabled — — — — PERT/PPST Disabled IOC5 — — — PERT/PPST Disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 85 VSSA — — — — — — — RXD0 — — — PERS/PPSS TXD0 — — — PERS/PPSS RXD1 — — — PERS/PPSS TXD1 — — — PERS/PPSS MISO0 — — — PERS/PPSS MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 86 — — — — PERM/PPSM Disabled — — — — PERM/PPSM Disabled KWJ7 — — — PERJ/PPSJ The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 87: S12G96 And S12G128
Figure 1-15. 48-Pin LQFP Pinout for S12G96 and S12G128 Table 1-20. 48-Pin LQFP Pinout for S12G96 and S12G128 Function Internal Pull <----lowest-----PRIORITY-----highest----> Resistor Power Supply Reset Package Pin CTRL Func. Func. Func Func State RESET — — — — PULLUP MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 88 — — PERT/PPST Disabled PAD0 KWAD0 — — PER1AD/PPS1AD Disabled PAD8 KWAD8 — — PER0AD/PPS0AD Disabled PAD1 KWAD1 — — PER1AD/PPS1AD Disabled PAD9 KWAD9 — PER0AD/PPS0AD Disabled PAD2 KWAD2 — — PER1AD/PPS1AD Disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 89 PERS/PPSS API_EXTC ECLK — PERS/PPSS RXD2 RXCAN — — PERM/PPSM Disabled TXD2 TXCAN — — PERM/PPSM Disabled The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 90 PAD5/KWAD5/AN5 S12G96 PAD12/KWAD12 VSSX S12G128 PAD4/KWAD4/AN4 EXTAL/PE0 PAD11/KWAD11/AN11 XTAL/PE1 PAD3/KWAD3/AN3 64-Pin LQFP TEST PAD10/KWAD10/AN10 PAD2/KWAD2/AN2 MISO1/KWJ0/PJ0 PAD9/KWAD9/AN9 MOSI1/KWJ1/PJ1 SCK1/KWJ2/PJ2 PAD1/KWAD1/AN1 SS1/KWJ3/PJ3 PAD8/KWAD8/AN8 BKGD PAD0/KWAD0/AN0 Figure 1-16. 64-Pin LQFP Pinout for S12G96 and S12G128 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 91 — PERP/PPSP Disabled KWP6 PWM6 — — PERP/PPSP Disabled KWP7 PWM7 — — PERP/PPSP Disabled IOC7 — — — PERT/PPST Disabled IOC6 — — — PERT/PPST Disabled IOC5 — — — PERT/PPST Disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 92 VSSA — — — — — — — RXD0 — — — PERS/PPSS TXD0 — — — PERS/PPSS RXD1 — — — PERS/PPSS TXD1 — — — PERS/PPSS MISO0 — — — PERS/PPSS MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 93 Disabled RXD2 — — — PERM/PPSM Disabled TXD2 — — — PERM/PPSM Disabled KWJ7 — — PERJ/PPSJ The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 94 VSSX1 PAD5/KWAD5/AN5 S12G128 EXTAL/PE0 PAD12/KWAD12 PAD4/KWAD4/AN4 100-Pin LQFP XTAL/PE1 PAD11/KWAD11/AN11 TEST PAD3/KWAD3/AN3 PAD10/KWAD10/AN10 PAD2/KWAD2/AN2 PAD9/KWAD9/AN9 PAD1/KWAD1/AN1 MISO1/KWJ0/PJ0 PAD8/KWAD8/AN8 MOSI1/KWJ1/PJ1 PAD0/KWAD0/AN0 SCK1/KWJ2/PJ2 SS1/KWJ3/PJ3 BKGD ECLK/PB0 Figure 1-17. 100-Pin LQFP Pinout for S12G96 and S12G128 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 95: Api_Extc
— PERJ/PPSJ KWJ1 MOSI1 — PERJ/PPSJ KWJ2 SCK1 — PERJ/PPSJ KWJ3 — PERJ/PPSJ BKGD MODC — — PUCR/BKPUE ECLK — — PUCR/PUPBE Disabled API_EXTC — — PUCR/PUPBE Disabled ECLKX2 — — PUCR/PUPBE Disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 96 — PUCR/PUPBE Disabled — — — PUCR/PUPCE Disabled — — — PUCR/PUPCE Disabled — — — PUCR/PUPCE Disabled — — — PUCR/PUPCE Disabled PAD0 KWAD0 — PER1AD/PPS1AD Disabled PAD8 KWAD8 — PER0AD/PPS0AD Disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 97 PUCR/PUPDE Disabled — — — PUCR/PUPDE Disabled — — — PUCR/PUPDE Disabled — — — PUCR/PUPDE Disabled RXD0 — — PERS/PPSS TXD0 — — PERS/PPSS RXD1 — — PERS/PPSS TXD1 — — PERS/PPSS MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 98 — — PUCR/PUPDE Disabled RXD2 — — PERM/PPSM Disabled TXD2 — — PERM/PPSM Disabled KWJ7 — PERJ/PPSJ The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 99: S12Ga96 And S12Ga128
Figure 1-18. 48-Pin LQFP Pinout for S12GA96 and S12GA128 Table 1-23. 48-Pin LQFP Pinout for S12GA96 and S12GA128 Function Internal Pull <----lowest-----PRIORITY-----highest----> Resistor Power Supply Reset Package Pin CTRL Func. Func. Func Func State RESET — — — — PULLUP MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 100 — — PERT/PPST Disabled PAD0 KWAD0 — — PER1AD/PPS1AD Disabled PAD8 KWAD8 — — PER0AD/PPS0AD Disabled PAD1 KWAD1 — — PER1AD/PPS1AD Disabled PAD9 KWAD9 — PER0AD/PPS0AD Disabled PAD2 KWAD2 — — PER1AD/PPS1AD Disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 101 PERS/PPSS API_EXTC ECLK — PERS/PPSS RXD2 RXCAN — — PERM/PPSM Disabled TXD2 TXCAN — — PERM/PPSM Disabled The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 102 PAD5/KWAD5/AN5 S12GA96 PAD12/KWAD12 VSSX S12GA128 PAD4/KWAD4/AN4 EXTAL/PE0 PAD11/KWAD11/AN11 XTAL/PE1 PAD3/KWAD3/AN3 64-Pin LQFP TEST PAD10/KWAD10/AN10 PAD2/KWAD2/AN2 MISO1/KWJ0/PJ0 PAD9/KWAD9/AN9 MOSI1/KWJ1/PJ1 SCK1/KWJ2/PJ2 PAD1/KWAD1/AN1 SS1/KWJ3/PJ3 PAD8/KWAD8/AN8 BKGD PAD0/KWAD0/AN0 Figure 1-19. 64-Pin LQFP Pinout for S12GA96 and S12GA128 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 103 — PERP/PPSP Disabled KWP6 PWM6 — — PERP/PPSP Disabled KWP7 PWM7 — — PERP/PPSP Disabled IOC7 — — — PERT/PPST Disabled IOC6 — — — PERT/PPST Disabled IOC5 — — — PERT/PPST Disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 104 VSSA — — — — — — — RXD0 — — — PERS/PPSS TXD0 — — — PERS/PPSS RXD1 — — — PERS/PPSS TXD1 — — — PERS/PPSS MISO0 — — — PERS/PPSS MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 105 Disabled RXD2 — — — PERM/PPSM Disabled TXD2 — — — PERM/PPSM Disabled KWJ7 — — PERJ/PPSJ The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 106 VSSX1 PAD5/KWAD5/AN5 S12GA128 EXTAL/PE0 PAD12/KWAD12 PAD4/KWAD4/AN4 100-Pin LQFP XTAL/PE1 PAD11/KWAD11/AN11 TEST PAD3/KWAD3/AN3 PAD10/KWAD10/AN10 PAD2/KWAD2/AN2 PAD9/KWAD9/AN9 PAD1/KWAD1/AN1 MISO1/KWJ0/PJ0 PAD8/KWAD8/AN8 MOSI1/KWJ1/PJ1 PAD0/KWAD0/AN0 SCK1/KWJ2/PJ2 SS1/KWJ3/PJ3 BKGD ECLK/PB0 Figure 1-20. 100-Pin LQFP Pinout for S12GA96 and S12GA128 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 107 — PERJ/PPSJ KWJ1 MOSI1 — PERJ/PPSJ KWJ2 SCK1 — PERJ/PPSJ KWJ3 — PERJ/PPSJ BKGD MODC — — PUCR/BKPUE ECLK — — PUCR/PUPBE Disabled API_EXTC — — PUCR/PUPBE Disabled ECLKX2 — — PUCR/PUPBE Disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 108 — PUCR/PUPBE Disabled — — — PUCR/PUPCE Disabled — — — PUCR/PUPCE Disabled — — — PUCR/PUPCE Disabled — — — PUCR/PUPCE Disabled PAD0 KWAD0 — PER1AD/PPS1AD Disabled PAD8 KWAD8 — PER0AD/PPS0AD Disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 109 PUCR/PUPDE Disabled — — — PUCR/PUPDE Disabled — — — PUCR/PUPDE Disabled — — — PUCR/PUPDE Disabled RXD0 — — PERS/PPSS TXD0 — — PERS/PPSS RXD1 — — PERS/PPSS TXD1 — — PERS/PPSS MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 110 — — PUCR/PUPDE Disabled RXD2 — — PERM/PPSM Disabled TXD2 — — PERM/PPSM Disabled KWJ7 — PERJ/PPSJ The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 111: S12G192 And S12G240
Figure 1-21. 48-Pin LQFP Pinout for S12G192 and S12G240 Table 1-26. 48-Pin LQFP Pinout for S12G192 and S12G240 Function Internal Pull <----lowest-----PRIORITY-----highest----> Resistor Power Supply Reset Package Pin CTRL Func. Func. Func Func State RESET — — — — PULLUP MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 112 — PERT/PPST Disabled PAD0 KWAD0 — — PER1AD/PPS1AD Disabled PAD8 KWAD8 — — PER0AD/PPS0AD Disabled PAD1 KWAD1 — — PER1AD/PPS1AD Disabled PAD9 KWAD9 — — PER0AD/PPS0AD Disabled PAD2 KWAD2 — — PER1AD/PPS1AD Disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 113 PERS/PPSS API_EXTC ECLK — PERS/PPSS RXD2 RXCAN — — PERM/PPSM Disabled TXD2 TXCAN — — PERM/PPSM Disabled The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 114 PAD5/KWAD5/AN5 S12G192 PAD12/KWAD12/AN12 VSSX S12G240 PAD4/KWAD4/AN4 EXTAL/PE0 PAD11/KWAD11/AN11 XTAL/PE1 PAD3/KWAD3/AN3 64-Pin LQFP TEST PAD10/KWAD10/AN10 PAD2/KWAD2/AN2 MISO1/KWJ0/PJ0 PAD9/KWAD9/AN9 MOSI1/KWJ1/PJ1 SCK1/KWJ2/PJ2 PAD1/KWAD1/AN1 SS1/KWJ3/PJ3 PAD8/KWAD8/AN8 BKGD PAD0/KWAD0/AN0 Figure 1-22. 64-Pin LQFP Pinout for S12G192 and S12G240 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 115 — PERP/PPSP Disabled KWP6 PWM6 — — PERP/PPSP Disabled KWP7 PWM7 — — PERP/PPSP Disabled IOC7 — — — PERT/PPST Disabled IOC6 — — — PERT/PPST Disabled IOC5 — — — PERT/PPST Disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 116 VSSA — — — — — — — RXD0 — — — PERS/PPSS TXD0 — — — PERS/PPSS RXD1 — — — PERS/PPSS TXD1 — — — PERS/PPSS MISO0 — — — PERS/PPSS MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 117 Disabled RXD2 — — — PERM/PPSM Disabled TXD2 — — — PERM/PPSM Disabled KWJ7 — — PERJ/PPSJ The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 118 VSSX1 PAD5/KWAD5/AN5 S12G240 EXTAL/PE0 PAD12/KWAD12/AN12 PAD4/KWAD4/AN4 100-Pin LQFP XTAL/PE1 PAD11/KWAD11/AN11 TEST PAD3/KWAD3/AN3 PAD10/KWAD10/AN10 PAD2/KWAD2/AN2 PAD9/KWAD9/AN9 PAD1/KWAD1/AN1 MISO1/KWJ0/PJ0 PAD8/KWAD8/AN8 MOSI1/KWJ1/PJ1 PAD0/KWAD0/AN0 SCK1/KWJ2/PJ2 SS1/KWJ3/PJ3 BKGD ECLK/PB0 Figure 1-23. 100-Pin LQFP Pinout for S12G192 and S12G240 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 119 — PERJ/PPSJ KWJ1 MOSI1 — PERJ/PPSJ KWJ2 SCK1 — PERJ/PPSJ KWJ3 — PERJ/PPSJ BKGD MODC — — PUCR/BKPUE ECLK — — PUCR/PUPBE Disabled API_EXTC — — PUCR/PUPBE Disabled ECLKX2 — — PUCR/PUPBE Disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 120 — PUCR/PUPBE Disabled — — — PUCR/PUPCE Disabled — — — PUCR/PUPCE Disabled — — — PUCR/PUPCE Disabled — — — PUCR/PUPCE Disabled PAD0 KWAD0 — PER1AD/PPS1AD Disabled PAD8 KWAD8 — PER0AD/PPS0AD Disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 121 PUCR/PUPDE Disabled — — — PUCR/PUPDE Disabled — — — PUCR/PUPDE Disabled — — — PUCR/PUPDE Disabled RXD0 — — PERS/PPSS TXD0 — — PERS/PPSS RXD1 — — PERS/PPSS TXD1 — — PERS/PPSS MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 122 — — PUCR/PUPDE Disabled RXD2 — — PERM/PPSM Disabled TXD2 — — PERM/PPSM Disabled KWJ7 — PERJ/PPSJ The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 123: S12Ga192 And S12Ga240
Figure 1-24. 48-Pin LQFP Pinout for S12GA192 and S12GA240 Table 1-29. 48-Pin LQFP Pinout for S12GA192 and S12GA240 Function Internal Pull <----lowest-----PRIORITY-----highest----> Resistor Power Supply Reset Package Pin CTRL Func. Func. Func Func State RESET — — — — PULLUP MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 124 — — PERT/PPST Disabled PAD0 KWAD0 — — PER1AD/PPS1AD Disabled PAD8 KWAD8 — — PER0AD/PPS0AD Disabled PAD1 KWAD1 — — PER1AD/PPS1AD Disabled PAD9 KWAD9 — PER0AD/PPS0AD Disabled PAD2 KWAD2 — — PER1AD/PPS1AD Disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 125 PERS/PPSS API_EXTC ECLK — PERS/PPSS RXD2 RXCAN — — PERM/PPSM Disabled TXD2 TXCAN — — PERM/PPSM Disabled The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 126 PAD5/KWAD5/AN5 S12GA192 PAD12/KWAD12/AN12 VSSX S12GA240 PAD4/KWAD4/AN4 EXTAL/PE0 PAD11/KWAD11/AN11/AMP0 XTAL/PE1 PAD3/KWAD3/AN3 64-Pin LQFP TEST PAD10/KWAD10/AN10/DACU1/AMP1 PAD2/KWAD2/AN2 MISO1/KWJ0/PJ0 PAD9/KWAD9/AN9 MOSI1/KWJ1/PJ1 SCK1/KWJ2/PJ2 PAD1/KWAD1/AN1 SS1/KWJ3/PJ3 PAD8/KWAD8/AN8 BKGD PAD0/KWAD0/AN0 Figure 1-25. 64-Pin LQFP Pinout for S12GA192 and S12GA240 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 127 — PERP/PPSP Disabled KWP6 PWM6 — — PERP/PPSP Disabled KWP7 PWM7 — — PERP/PPSP Disabled IOC7 — — — PERT/PPST Disabled IOC6 — — — PERT/PPST Disabled IOC5 — — — PERT/PPST Disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 128 VSSA — — — — — — — RXD0 — — — PERS/PPSS TXD0 — — — PERS/PPSS RXD1 — — — PERS/PPSS TXD1 — — — PERS/PPSS MISO0 — — — PERS/PPSS MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 129 Disabled RXD2 — — — PERM/PPSM Disabled TXD2 — — — PERM/PPSM Disabled KWJ7 — — PERJ/PPSJ The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 130 VSSX1 PAD5/KWAD5/AN5 S12GA240 EXTAL/PE0 PAD12/KWAD12/AN12 PAD4/KWAD4/AN4 100-Pin LQFP XTAL/PE1 PAD11/KWAD11/AN11/AMP0 TEST PAD3/KWAD3/AN3 PAD10/KWAD10/AN10/AMP1 PAD2/KWAD2/AN2 PAD9/KWAD9/AN9 PAD1/KWAD1/AN1 MISO1/KWJ0/PJ0 PAD8/KWAD8/AN8 MOSI1/KWJ1/PJ1 PAD0/KWAD0/AN0 SCK1/KWJ2/PJ2 SS1/KWJ3/PJ3 BKGD ECLK/PB0 Figure 1-26. 100-Pin LQFP Pinout for S12GA192 and S12GA240 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 131 — PERJ/PPSJ KWJ1 MOSI1 — PERJ/PPSJ KWJ2 SCK1 — PERJ/PPSJ KWJ3 — PERJ/PPSJ BKGD MODC — — PUCR/BKPUE ECLK — — PUCR/PUPBE Disabled API_EXTC — — PUCR/PUPBE Disabled ECLKX2 — — PUCR/PUPBE Disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 132 — PUCR/PUPBE Disabled — — — PUCR/PUPCE Disabled — — — PUCR/PUPCE Disabled — — — PUCR/PUPCE Disabled — — — PUCR/PUPCE Disabled PAD0 KWAD0 — PER1AD/PPS1AD Disabled PAD8 KWAD8 — PER0AD/PPS0AD Disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 133 PUCR/PUPDE Disabled — — — PUCR/PUPDE Disabled — — — PUCR/PUPDE Disabled — — — PUCR/PUPDE Disabled RXD0 — — PERS/PPSS TXD0 — — PERS/PPSS RXD1 — — PERS/PPSS TXD1 — — PERS/PPSS MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 134 — — PUCR/PUPDE Disabled RXD2 — — PERM/PPSM Disabled TXD2 — — PERM/PPSM Disabled KWJ7 — PERJ/PPSJ The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 135 — PUCR/PUPAE Disabled KWJ0 MISO1 — PERJ/PPSJ KWJ1 MOSI1 — PERJ/PPSJ KWJ2 SCK1 — PERJ/PPSJ KWJ3 — PERJ/PPSJ BKGD MODC — — PUCR/BKPUE ECLK — — PUCR/PUPBE Disabled API_EXTC — — PUCR/PUPBE Disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 136 — PUCR/PUPBE Disabled — — — PUCR/PUPBE Disabled — — — PUCR/PUPCE Disabled — — — PUCR/PUPCE Disabled — — — PUCR/PUPCE Disabled — — — PUCR/PUPCE Disabled PAD0 KWAD0 — PER1AD/PPS1AD Disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 137 — — — — PUCR/PUPDE Disabled — — — PUCR/PUPDE Disabled — — — PUCR/PUPDE Disabled — — — PUCR/PUPDE Disabled RXD0 — — PERS/PPSS TXD0 — — PERS/PPSS RXD1 — — PERS/PPSS MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 138: System Clock Description
These are described in 1.10.2 Low Power Operation. Some modules feature a software programmable option to freeze the module status whilst the background debug module is active to facilitate debugging. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 139: Chip Configuration Summary
ROM. BDM firmware waits for additional serial commands through the BKGD pin. 1.10.2 Low Power Operation The MC9S12G has two static low-power modes Pseudo Stop and Stop Mode. For a detailed description refer to S12CPMU section. 1.11 Security The MCU security mechanism prevents unauthorized access to the Flash memory.
Page 140: Interrupt Vectors
Vector base + $D8 SPI0 I bit SPI0CR1 (SPIE, SPTIE) Vector base+ $D6 SCI0 I bit SCI0CR2 (TIE, TCIE, RIE, ILIE) Vector base + $D4 SCI1 I bit SCI1CR2 (TIE, TCIE, RIE, ILIE) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 141 — None 16 bits vector address based Only available if the 8 channel timer module is instantiated on the device Only available if the 8 channel timer module is instantiated on the device MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 142: Effects Of Reset
The FOPT register is loaded from the Flash configuration field byte at global address 0x3_FF0E during the reset sequence. Table 1-36. Initial COP Rate Configuration NV[2:0] in CR[2:0] in FOPT Register CPMUCOP Register MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 143: Autonomous Clock (Aclk) Configuration
The ADC temperature sensor is only available on S12GA192 and S12GA240 devices. 1. See Chapter 10, “S12 Clock, Reset and Power Management Unit (S12CPMU)” 2. See Section 10.3.2.15, “Autonomous Clock Trimming Register (CPMUACLKTR)” MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 144: Adc Result Reference
On all S12G devices except for the S12GA192 and the S12GA240 the external VRH signal is directly connected to the ADC’s VRH signal input. The ADC’s VRL input is connected to VSSA. (see Figure 1-27). 1. The format of the stored V reference value is still subject to change. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 145: Bdm Clock Source Connectivity
S12GA128, S12G192, S12G240 VSSA S12GA192, S12GA240 VRH_INT VRL_INT VSSA VSSA Figure 1-27. ADC VRH/VRL Signal Connection 1.19 BDM Clock Source Connectivity The BDM clock is mapped to the VCO clock divided by 8. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 146 Device Overview MC9S12G-Family MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 147: Chapter 2 Port Integration Module (S12Gpimv1)
Package terminal with a unique number defined in the device pinout section Signal Input or output line of a peripheral module or general-purpose I/O function arbitrating for a dedicated pin Port Group of general-purpose I/O pins sharing peripheral signals MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 148: Overview
Package code register preset by factory related to package in use, writable once after reset. Also includes bit to reprogram routing of API_EXTCLK in all packages. • Control register for free-running clock outputs • MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 149: Block Diagram
I/O port pins for each group in the largest offered package option. Table 2-3. Port Pin Availability (in largest package) per Device Device Group Port (100 pin) (64 pin) (48 pin) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 150: Package Code
Section 2.4, “PIM Ports - Memory Map and Register Definition”). For example pin PAD15: Signal [PT0AD7] is bit 7 of register PT0AD; other related register bits of this pin are PTI0AD7, DDR0AD7, PER0AD7, PPS0AD7, PIE0AD7 and PIF0AD7. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 151 Port Integration Module (S12GPIMV1) NOTE If there is more than one signal associated with a pin, the priority is indicated by the position in the table from top (highest priority) to bottom (lowest priority). MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 152: Pim Routing - Functional Description
[PC5] I/O GPIO ? ? ? PC4-PC2 AN15-AN13 ADC analog [PC4:PC2] I/O GPIO ? ? ? PC1-PC0 AN11-AN10 ADC analog [PC1:PC0] I/O GPIO ? ? ? PD7-PD0 [PD7:PD0] I/O GPIO ? ? ? MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 153 ? ? ? ? ? ? ? ? ? [PTT0] I/O GPIO ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 154 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? [PTS0] I/O GPIO ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 155 ? ? ? ? RXD2 SCI receive ? ? ? RXD1 SCI receive [PTM0] I/O GPIO ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 156 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? [PTP0]/ I/O GPIO with interrupt ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? KWP0 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 157 ? ? ? ? ? ? ? ? ? ? ? ? PWM6 I/O Timer channel ? ? ? [PTJ0]/ I/O GPIO with interrupt ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? KWJ0 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 158 I/O GPIO with interrupt ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? KWAD9 PAD8 ADC analog ? ? ? ? ? ? ? ? ? ? ? ? MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 159 ? ? ? ? ? ? ? ? ? [PT1AD2: I/O GPIO with interrupt ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? PT1AD0]/ KWAD2- KWAD0 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 160 The general-purpose output is always of lowest priority if no other signal is enabled. Peripheral input signals on shared pins are always connected monitoring the pin level independent of their use. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 161: Pin Bkgd
ECLK signal forces the I/O state to an output. • Signal priority: 100 LQFP: ECLK > GPO 2.3.4 Pins PC7-0 NOTE • When using AMPM1, AMPP1 or DACU1 please refer to section 2.6.1, “Initialization”. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 162 The routed ADC function has no effect on the output state. Refer to NOTE/2-163 for input buffer control. • Signal priority: 100 LQFP: GPO MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 163: Pins Pd7-0
I/O or as timer output. The use case for the ACMP timer link requires the timer input capture function to be enabled. • Signal priority: 48/64/100 LQFP: IOC5 > GPO MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 164 • The TIM channel 0 signal is mapped to this pin when used with the timer function. The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. • Signal priority: 100 LQFP: IOC0 > GPO Others: XIRQ > IOC0 > GPO MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 165: Pins Ps7-0
I/O state will be forced to output. • Signal priority: 20 TSSOP: MOSI0 > IOC2 > GPO 32 LQFP: MOSI0 > IOC4 > GPO Others: MOSI0 > GPO MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 166 • Except 20 TSSOP: The SCI0 RXD signal is mapped to this pin when used with the SCI function. If the SCI0 RXD signal is enabled the I/O state will be forced to be input. • Signal priority: 20 TSSOP: GPO Others: RXD0 > GPO MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 167: Pins Pm3-0
PWM function. The enabled PWM channel forces the I/O state to be an output. • 48/64/100 LQFP: Pin interrupts can be generated if enabled in input or output mode. • Signal priority: 48/64/100 LQFP: PWM > GPO MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 168 • Except 20 TSSOP: Pin interrupts can be generated if enabled in input or output mode. • Signal priority: Except 100 LQFP and 20 TSSOP: PWM0 > API_EXTCLK > GPO 100 LQFP: PWM0 > GPO MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 169: Pins Pj7-0
• Except 20 TSSOP and 32 LQFP: Pin interrupts can be generated if enabled in input or output mode. • Signal priority: 48 LQFP: SCK1 > IOC7 > GPO 64/100 LQFP: SCK1 > GPO MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 170: Pins Ad15-0
Taking the availability of the different sources on each pin into account the following logic equation must be true to activate the digital input buffer for general-purpose input use: IBEx = ( (ATDDIENH/L[IENx]=1) OR (ATDCTL1[ETRIGSEL]=0 AND ATDCTL2[ETRIGE]=1) OR (PRR1[PRR1AN]=1) ) AND (ACDIEN=1) Eqn. 2-1 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 171 The ADC function has no effect on the output state. Refer to NOTE/2-172 for input buffer control. • 64/100 LQFP: Pin interrupts can be generated if enabled in digital input or output mode. • Signal priority: 64/100 LQFP: GPO MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 172 • 48/64/100 LQFP: Pin interrupts can be generated if enabled in digital input or output mode. • Signal priority: 48/64 LQFP: AMP1 > DACU1 > GPO 100 LQFP: AMP1 > GPO MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 173 The ADC function has no effect on the output state. Refer to NOTE/2-172 for input buffer control. • Except 20 TSSOP: Pin interrupts can be generated if enabled in digital input or output mode. • Signal priority: Except 20 TSSOP: GPO MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 174 Section 2.6.4, “ADC External Triggers ETRIG3-0”. • Pin interrupts can be generated if enabled in digital input or output mode. • Signal priority: 20 TSSOP: RXD0 > IOC2 > PWM2 > GPO Others: GPO MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 175 The ADC function has no effect on the output state. Refer to NOTE/2-172 for input buffer control. • Pin interrupts can be generated if enabled in digital input or output mode. • Signal priority: MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 176: Pim Ports - Memory Map And Register Definition
0x50 2.4.3.11/2-203 0x000D Reserved 0x00 0x000E Non-PIM address range 0x001B 0x001C ECLKCTL—ECLK Control Register 0xC0 2.4.3.12/2-205 0x001D Reserved 0x00 0x001E IRQCR—IRQ Control Register 0x00 2.4.3.13/2-205 0x001F Reserved 0x00 0x0020 Non-PIM address range 0x023F MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 177 0x025C PERP—Port P Pull Device Enable Register 0x00 2.4.3.37/2-222 0x025D PPSP—Port P Polarity Select Register 0x00 2.4.3.38/2-223 0x025E PIEP—Port P Interrupt Enable Register 0x00 2.4.3.39/2-224 0x025F PIFP—Port P Interrupt Flag Register 0x00 2.4.3.40/2-224 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 178 In any other case this address is reserved. Refer to device memory map to determine related module. Read always returns logic level on pins. Routing takes only effect if the PKGCR is set to 20 TSSOP. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 179: Register Map
PORTC 0x0005 PORTD 0x0006 DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 DDRC 0x0007 DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 DDRD 0x0008 PORTE 0x0009 DDRE1 DDRE0 DDRE = Unimplemented or Reserved MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 180 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 DDRT 0x0243 Reserved 0x0244 PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 PERT 0x0245 PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 PPST = Unimplemented or Reserved MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 181 PRR0T20 PRR0S1 PRR0S0 PRR0 0x0250 PTM3 PTM2 PTM1 PTM0 0x0251 PTIM3 PTIM2 PTIM1 PTIM0 PTIM 0x0252 DDRM3 DDRM2 DDRM1 DDRM0 DDRM 0x0253 Reserved 0x0254 PERM3 PERM2 PERM1 PERM0 PERM = Unimplemented or Reserved MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 182 0x0268 PTJ7 PTJ6 PTJ5 PTJ4 PTJ3 PTJ2 PTJ1 PTJ0 0x0269 PTIJ7 PTIJ6 PTIJ5 PTIJ4 PTIJ3 PTIJ2 PTIJ1 PTIJ0 PTIJ 0x026A DDRJ7 DDRJ6 DDRJ5 DDRJ4 DDRJ3 DDRJ2 DDRJ1 DDRJ0 DDRJ = Unimplemented or Reserved MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 183 Reserved for RVACTL on G(A)240 and G(A)192 Reserved 0x0277 PRR1AN PRR1 0x0278 PER0AD7 PER0AD6 PER0AD5 PER0AD4 PER0AD3 PER0AD2 PER0AD1 PER0AD0 PER0AD 0x0279 PER1AD7 PER1AD6 PER1AD5 PER1AD4 PER1AD3 PER1AD2 PER1AD1 PER1AD0 PER1AD = Unimplemented or Reserved MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 184 Global Address Bit 7 Bit 0 Register Name 0x0000–0x0007 Reserved 0x0008 PORTE 0x0009 DDRE1 DDRE0 DDRE 0x000A–0x000B Non-PIM Non-PIM Address Range Address Range 0x000C BKPUE PDPEE PUCR 0x000D Reserved = Unimplemented or Reserved MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 185 PERT4 PERT3 PERT2 PERT1 PERT0 PERT 0x0245 PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 PPST 0x0246 Reserved 0x0247 Reserved 0x0248 PTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0 = Unimplemented or Reserved MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 186 DDRM1 DDRM0 DDRM 0x0253 Reserved 0x0254 PERM3 PERM2 PERM1 PERM0 PERM 0x0255 PPSM3 PPSM2 PPSM1 PPSM0 PPSM 0x0256 WOMM3 WOMM2 WOMM1 WOMM0 WOMM 0x0257 APICLKS7 PKGCR2 PKGCR1 PKGCR0 PKGCR = Unimplemented or Reserved MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 187 PTJ6 PTJ5 PTJ4 PTJ3 PTJ2 PTJ1 PTJ0 0x0269 PTIJ7 PTIJ6 PTIJ5 PTIJ4 PTIJ3 PTIJ2 PTIJ1 PTIJ0 PTIJ 0x026A DDRJ7 DDRJ6 DDRJ5 DDRJ4 DDRJ3 DDRJ2 DDRJ1 DDRJ0 DDRJ 0x026B Reserved = Unimplemented or Reserved MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 188 PER0AD7 PER0AD6 PER0AD5 PER0AD4 PER0AD3 PER0AD2 PER0AD1 PER0AD0 PER0AD 0x0279 PER1AD7 PER1AD6 PER1AD5 PER1AD4 PER1AD3 PER1AD2 PER1AD1 PER1AD0 PER1AD 0x027A PPS0AD7 PPS0AD6 PPS0AD5 PPS0AD4 PPS0AD3 PPS0AD2 PPS0AD1 PPS0AD0 PPS0AD = Unimplemented or Reserved MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 189 Global Address Bit 7 Bit 0 Register Name 0x0000–0x0007 Reserved 0x0008 PORTE 0x0009 DDRE1 DDRE0 DDRE 0x000A–0x000B Non-PIM Non-PIM Address Range Address Range 0x000C BKPUE PDPEE PUCR 0x000D Reserved = Unimplemented or Reserved MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 190 0x0244 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 PERT 0x0245 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 PPST 0x0246 Reserved 0x0247 Reserved 0x0248 PTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0 = Unimplemented or Reserved MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 191 PTM0 0x0251 PTIM1 PTIM0 PTIM 0x0252 DDRM1 DDRM0 DDRM 0x0253 Reserved 0x0254 PERM1 PERM0 PERM 0x0255 PPSM1 PPSM0 PPSM 0x0256 WOMM1 WOMM0 WOMM 0x0257 APICLKS7 PKGCR2 PKGCR1 PKGCR0 PKGCR = Unimplemented or Reserved MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 192 Reserved for ACMP Reserved 0x0262–0x0267 Reserved 0x0268 PTJ3 PTJ2 PTJ1 PTJ0 0x0269 PTIJ3 PTIJ2 PTIJ1 PTIJ0 PTIJ 0x026A DDRJ3 DDRJ2 DDRJ1 DDRJ0 DDRJ 0x026B Reserved 0x026C PERJ3 PERJ2 PERJ1 PERJ0 PERJ = Unimplemented or Reserved MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 193 PER0AD3 PER0AD2 PER0AD1 PER0AD0 PER0AD 0x0279 PER1AD7 PER1AD6 PER1AD5 PER1AD4 PER1AD3 PER1AD2 PER1AD1 PER1AD0 PER1AD 0x027A PPS0AD3 PPS0AD2 PPS0AD1 PPS0AD0 PPS0AD 0x027B PPS1AD7 PPS1AD6 PPS1AD5 PPS1AD4 PPS1AD3 PPS1AD2 PPS1AD1 PPS1AD0 PPS1AD = Unimplemented or Reserved MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 194: Register Descriptions
• Pull-device availability, pull-device polarity, wired-or mode, key-wakeup functionality are independent of the prioritization unless noted differently in section Section 2.3, “PIM Routing - Functional description”. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 195 2.4.3.2 Port B Data Register (PORTB) Address 0x0001 (G1) Access: User read/write Reset Address 0x0001 (G2, G3) Access: User read only Reset Figure 2-3. Port B Data Register (PORTB) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 196 Table 2-24. DDRA Register Field Descriptions Field Description Port A Data Direction— DDRA This bit determines whether the associated pin is an input or output. 1 Associated pin configured as output 0 Associated pin configured as input MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 197 Access: User read/write Reset Address 0x0004 (G2, G3) Access: User read only Reset Figure 2-6. Port C Data Register (PORTC) Read: Anytime. The data source is depending on the data direction value. Write: Anytime MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 198 If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the buffered pin input state is read. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 199 Access: User read/write DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 Reset Address 0x0007 (G2, G3) Access: User read only Reset Figure 2-9. Port D Data Direction Register (DDRD) Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 200 2.4.3.10 Port E Data Direction Register (DDRE) Address 0x0009 Access: User read/write DDRE1 DDRE0 Reset Figure 2-11. Port E Data Direction Register (DDRE) Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 201 This bit configures whether a pullup device is activated on all associated port input pins. If a pin is used as output this bit has no effect. 1 Pullup devices enabled 0 Pullup devices disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 202 This bit configures whether a pullup device is activated on all associated port input pins. If a pin is used as output this bit has no effect. 1 Pullup devices enabled 0 Pullup devices disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 203 00010 ECLK rate = bus clock rate divided by 3,... 11111 ECLK rate = bus clock rate divided by 32 2.4.3.13 IRQ Control Register (IRQCR) Address 0x001E Access: User read/write IRQE IRQEN Reset Figure 2-14. IRQ Control Register (IRQCR) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 204 Write: Only in special mode These reserved registers are designed for factory test purposes only and are not intended for general user access. Writing to these registers when in special mode can alter the module’s functionality. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 205 PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 Reset Address 0x0241 (G3) Access: User read only PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 Reset Figure 2-17. Port T Input Register (PTIT) Read: Anytime Write:Never MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 206 Table 2-37. DDRT Register Field Descriptions Field Description Port T data direction— DDRT This bit determines whether the pin is a general-purpose input or output. 1 Associated pin configured as output 0 Associated pin configured as input MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 207 This bit controls whether a pull device on the associated port input pin is active. The polarity is selected by the related polarity select register bit. If this pin is used as XIRQ only a pullup device can be enabled. 1 Pull device enabled 0 Pull device disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 208 Address 0x0248 Access: User read/write PTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0 Figure 2-21. Port S Data Register (PTS) Read: Anytime. The data source is depending on the data direction value. Write: Anytime MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 209 2.4.3.22 Port S Data Direction Register (DDRS) Address 0x024A Access: User read/write DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 Reset Figure 2-23. Port S Data Direction Register (DDRS) Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 210 2.4.3.24 Port S Polarity Select Register (PPSS) Address 0x024D Access: User read/write PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0 Reset Figure 2-25. Port S Polarity Select Register (PPSS) Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 211 Routing takes only effect if PKGCR is set to select the 20 TSSOP package. Address 0x024F Access: User read/write PRR0P3 PRR0P2 PRR0T31 PRR0T30 PRR0T21 PRR0T20 PRR0S1 PRR0S0 Reset Figure 2-27. Pin Routing Register (PRR0) Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 212 Table 2-48. PWM2/ETRIG2 Routing Options PRR0P2 PWM2/ETRIG2 Associated Pin PS4 - PWM2, ETRIG2 PAD4 - PWM2, ETRIG2 Table 2-49. IOC3 Routing Options PRR0T31 PRR0T30 IOC3 Associated Pin PS6 - IOC3 PE1 - IOC3 PAD5 - IOC3 Reserved MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 213 If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the buffered pin input state is read. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 214 Address 0x0252 (G1, G2) Access: User read/write DDRM3 DDRM2 DDRM1 DDRM0 Reset Address 0x0252 (G3) Access: User read/write DDRM1 DDRM0 Reset Figure 2-30. Port M Data Direction Register (DDRM) Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 215 If a pin is used as output this bit has only effect if used in wired-or mode with a pullup device. If CAN is active the selection of a pulldown device on the RXCAN input will have no effect. 1 Pull device enabled 0 Pull device disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 216 Address 0x0256 (G1, G2) Access: User read/write WOMM3 WOMM2 WOMM1 WOMM0 Reset Address 0x0256 (G3) Access: User read/write WOMM1 WOMM0 Reset Figure 2-33. Port M Wired-Or Mode Register (WOMM) Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 217 Depending on the package selection the input buffers of non-bonded pins are disabled to avoid shoot-through current. Also a predefined signal routing will take effect. Refer also to Section 2.6.5, “Emulation of Smaller Packages”. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 218 Address 0x0258 (G3) Access: User read/write PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 Reset Figure 2-35. Port P Data Register (PTP) Read: Anytime. The data source is depending on the data direction value. Write: Anytime MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 219 Field Description Port P input data— PTIP A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit conditions on output pins. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 220 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 Reset Address 0x025C (G3) Access: User read/write PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 Reset Figure 2-38. Port P Pull Device Enable Register (PERP) Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 221 This bit selects a pullup or a pulldown device if enabled on the associated port input pin. This bit also selects the polarity of the active pin interrupt edge. 1 Pulldown device selected; rising edge selected 0 Pullup device selected; falling edge selected MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 222 Access: User read/write PIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0 Reset Address 0x025F (G3) Access: User read/write PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0 Reset Figure 2-41. Port P Interrupt Flag Register (PIFP) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 223 Writing a logic “1” to the corresponding bit field clears the flag. 1 Active edge on the associated bit has occurred 0 No active edge occurred MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 224 If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the buffered pin input state is read. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 225 Access: User read/write DDRJ7 DDRJ6 DDRJ5 DDRJ4 DDRJ3 DDRJ2 DDRJ1 DDRJ0 Reset Address 0x026A (G3) Access: User read/write DDRJ3 DDRJ2 DDRJ1 DDRJ0 Reset Figure 2-44. Port J Data Direction Register (DDRJ) Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 226 This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has no effect. The polarity is selected by the related polarity select register bit. 1 Pull device enabled 0 Pull device disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 227 Address 0x026E (G1, G2) Access: User read/write PIEJ7 PIEJ6 PIEJ5 PIEJ4 PIEJ3 PIEJ2 PIEJ1 PIEJ0 Reset Address 0x026E (G3) Access: User read/write PIEJ3 PIEJ2 PIEJ1 PIEJ0 Reset Figure 2-47. Port J Interrupt Enable Register (PIEJ) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 228 Writing a logic “1” to the corresponding bit field clears the flag. 1 Active edge on the associated bit has occurred 0 No active edge occurred MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 229 Access: User read/write PT1AD7 PT1AD6 PT1AD5 PT1AD4 PT1AD3 PT1AD2 PT1AD1 PT1AD0 Reset Figure 2-50. Port AD Data Register (PT1AD) Read: Anytime. The data source is depending on the data direction value. Write: Anytime MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 230 2.4.3.52 Port AD Input Register (PTI1AD) Address 0x0273 Access: User read only PTI1AD7 PTI1AD6 PTI1AD5 PTI1AD4 PTI1AD3 PTI1AD2 PTI1AD1 PTI1AD0 Reset Figure 2-52. Port AD Input Register (PTI1AD) Read: Anytime Write: Never MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 231 2.4.3.54 Port AD Data Direction Register (DDR1AD) Address 0x0275 Access: User read/write DDR1AD7 DDR1AD6 DDR1AD5 DDR1AD4 DDR1AD3 DDR1AD2 DDR1AD1 DDR1AD0 Reset Figure 2-54. Port AD Data Direction Register (DDR1AD) Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 232 The routing affects the analog signals and digital input trigger paths to the ADC. Refer to the related pin descriptions Section 2.3.4, “Pins PC7-0” and Section 2.3.12, “Pins AD15-0”. 1 AN inputs on port C 0 AN inputs on port AD MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 233 This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has no effect. The polarity is selected by the related polarity select register bit. 1 Pull device enabled 0 Pull device disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 234 Access: User read/write PPS0AD7 PPS0AD6 PPS0AD5 PPS0AD4 PPS0AD3 PPS0AD2 PPS0AD1 PPS0AD0 Reset Address 0x027A (G3) Access: User read/write PPS0AD3 PPS0AD2 PPS0AD1 PPS0AD0 Reset Figure 2-58. Port AD Polarity Select Register (PPS0AD) Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 235 This bit selects a pullup or a pulldown device if enabled on the associated port input pin. This bit also selects the polarity of the active pin interrupt edge. 1 Pulldown device selected; rising edge selected 0 Pullup device selected; falling edge selected MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 236 Port AD Interrupt Enable Register (PIE1AD) Read: Anytime Address 0x027D Access: User read/write PIE1AD7 PIE1AD6 PIE1AD5 PIE1AD4 PIE1AD3 PIE1AD2 PIE1AD1 PIE1AD0 Reset Figure 2-61. Port AD Interrupt Enable Register (PIE1AD) Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 237 Writing a logic “1” to the corresponding bit field clears the flag. 1 Active edge on the associated bit has occurred 0 No active edge occurred MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 238 Writing a logic “1” to the corresponding bit field clears the flag. 1 Active edge on the associated bit has occurred 0 No active edge occurred MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 239: Pim Ports - Functional Description
If the data direction register bits are set to 1, the contents of the data register is returned. This is independent of any other configuration (Figure 2-64). 2.5.2.2 Input Register (PTIx) This register is read-only and always returns the buffered state of the pin (Figure 2-64). MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 240 This register selects either a pullup or pulldown device if enabled. It becomes only active if the pin is used as an input. A pullup device can be activated if the pin is used as a wired-or output. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 241: Pin Configuration Summary
The configuration bit PS is used for two purposes: 1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled. 2. Select either a pullup or pulldown device if PE is active. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 242: Interrupts
IRQCR[IRQEN] bit must be set and the I bit cleared in the condition code register. The interrupt can be configured for level-sensitive or falling-edge-sensitive triggering. If IRQCR[IRQEN] is cleared while an interrupt is pending, the request will deassert. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 243 Sample count <= 4 (at active or passive level) and interrupt enabled (PIE=1) and interrupt flag not set (PIF=0). Glitch, filtered out, no interrupt flag set uncertain Valid pulse, interrupt flag set (min) t (max) PULSE PULSE Figure 2-65. Interrupt Glitch Filter (here: active low level selected) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 244: Initialization/Application Information
If the related PWM channel is enabled, the PWM signal as seen on the pin will drive the ETRIG input. If another signal of higher priority takes control of the pin or if on a port AD pin the input buffer is disabled, MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 245: Emulation Of Smaller Packages
These differences need to be accounted for when developing cross-functional code. 1. Except G(A)128/G(A)96 in 20 TSSOP: Internal routing of PWM to ETRIG is not available. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 246 Port Integration Module (S12GPIMV1) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 247: Chapter 3 5V Analog Comparator (Acmpv1)
Selectable interrupt on rising, falling, or rising and falling edges of comparator output • Option to output comparator signal on an external pin ACMPO • Option to trigger timer input capture events Block Diagram The block diagram of the ACMP is shown below. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 248: External Signals
The ACMP is held in shutdown mode either when disabled or during STOP mode. In this case the supply of the analog block is disconnected for power saving. ACMPO drives zero in shutdown mode. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 249: Memory Map And Register Definition
Enables the ACMP interrupt. 0 Interrupt disabled 1 Interrupt enabled ACMP Output Pin Enable— ACOPE Enables raw comparator output on external ACMPO pin. 0 ACMP output not available 1 ACMP output is driven out on ACMPO MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 250 0 ACMP disabled 1 ACMP enabled 3.6.2.2 ACMP Status Register (ACMPS) Address 0x0261 Access: User read/write ACIF Reset Figure 3-4. ACMP Status Register (ACMPS) Read: Anytime Write: ACIF: Anytime, write 1 to clear ACO: Never MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 251: Functional Description
An interrupt will be generated if the interrupt enable bit (ACMPC[ACIE]) and the interrupt flag (ACMPS[ACIF]) are both set. ACMPS[ACIF] is cleared by writing a 1. The raw comparator output signal ACMPO can be driven out on an external pin by setting the ACMPC[ACOPE] bit. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 252 5V Analog Comparator (ACMPV1) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 253: Chapter 4 Reference Voltage Attenuator (Rvav1)
Attenuation of ADC reference voltage with low long-term drift Block Diagram The block diagram of the RVA module is shown below. Refer to device overview section “ADC VRH/VRL Signal Connection” for connection of RVA to pins and ADC module. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 254: External Signals
STOP mode. 2. Bypass Mode The RVA is in bypass mode either when disabled or during STOP mode. In these cases the resistor ladder of the RVA is disconnected for power saving. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 255: Memory Map And Register Definition
Read: Anytime Write: Anytime Table 4-2. RVACTL Register Field Descriptions Field Description RVA On — RVAON This bit turns on the reference voltage attenuation. 0 RVA in bypass mode 1 RVA in attenuation mode MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 256: Functional Description
2. NOTE In attenuation mode the maximum ADC clock is reduced. Please refer to the conditions in appendix A “ATD Accuracy”, table “ATD Conversion Performance 5V range, RVA enabled”. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 257: Chapter 5 S12G Memory Map Controller (S12Gmmcv1)
(memories and peripherals). It arbitrates the bus accesses and determines all of the MCU’s memory maps. Furthermore, the S12GMMC is responsible for constraining memory accesses on secured devices and for selecting the MCU’s functional mode. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 258: Features
S12G devices can be secured to prohibit external access to the on-chip flash. The S12GMMC module determines the access permissions to the on-chip memories in secured and unsecured state. 5.1.5 Block Diagram Figure 5-1 shows a block diagram of the S12GMMC. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 259: External Signal Description
5.3.1 Module Memory Map A summary of the registers associated with the S12GMMC block is shown in Figure 5-2. Detailed descriptions of the registers and bits are given in the subsections that follow. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 260: Register Descriptions
This section consists of the S12GMMC control register descriptions in address order. 5.3.2.1 Mode Register (MODE) Address: 0x000B MODC Reset MODC 1. External signal (see Table 5-3). = Unimplemented or Reserved Figure 5-3. Mode Register (MODE) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 261 Read: Anytime Write: anytime in special SS, write-once in NS. This register determines the position of the 256 Byte direct page within the memory map.It is valid for both global and local mapping scheme. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 262 This bit maps internal NVM resources into the global address space. 0 Program flash is mapped to the global address range from 0x04000 to 0x07FFF. 1 NVM resources are mapped to the global address range from 0x04000 to 0x07FFF. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 263 The fixed 16KB page from 0x0000 to 0x3FFF is the page number 0xC. Parts of this page are covered by Registers, EEPROM and RAM space. See SoC Guide for details. The fixed 16KB page from 0x4000–0x7FFF is the page number 0xD. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 264: Functional Description
(PPAGE[3:0]) to page 16x16 KB blocks into the program page window located from address 0x8000 to address 0xBFFF in the local CPU memory map. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 265 The BDM program page index register (BDMPPR) is used only when the feature is enabled in BDM and, in the case the CPU is executing a firmware command which uses CPU instructions, or by a BDM hardware commands. See the BDM Block Guide for further details. (see Figure 5-10). MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 266 Global Address [17:0] Bit17 Bit0 Bit14 Bit13 BDMPPR Register [3:0] BDM Local Address [13:0] BDM FIRMWARE COMMAND Global Address [17:0] Bit17 Bit0 Bit14 Bit13 BDMPPR Register [3:0] CPU Local Address [13:0] Figure 5-10. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 267 Flash Space Flash Space Page 0xD Page 0xD 0x3_8000 Flash Space Flash Space Page 0xE Page 0xE 0x3_C000 Flash Space Flash Space Page 0xF Page 0xF 0x3_FFFF Figure 5-11. Local to Global Address Mapping MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 268: Unimplemented And Reserved Address Ranges
Register Space 0x003FF 0x00400- 0.5k 1.5k 0x005FF 0x00600- Reserved EEPROM 0x007FF 0x00800- 0x009FF 0x00A00- Reserved 0x00BFF 0x00C00- 0x00FFF 0x01000- Reserved 0x013FF 0x01400- Unimplemented 0x01FFF 0x02000- 0x2FFF 0x03000- 0x037FF 0x03800- Reserved 0x03BFF 0x03C00- 0x03FFF MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 269: Prioritization Of Memory Accesses
BDM accesses unless the BDM module has been stalled for more then 128 bus cycles. In this case the pending BDM access will be processed immediately. 5.4.5 Interrupts The S12GMMC does not generate any interrupts. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 270 S12G Memory Map Controller (S12GMMCV1) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 271: Chapter 6 Interrupt Module (S12Sintv1)
Table 6-2. Terminology Term Meaning Condition Code Register (in the CPU) Interrupt Service Routine Micro-Controller Unit 6.1.2 Features • Interrupt vector base register (IVBR) • One spurious interrupt vector (at address vector base + 0x0080). MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 272: Modes Of Operation
INT module. 1. The vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used as upper byte) and 0x00 (used as lower byte). MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 273: External Signal Description
This section describes in address order all the INT registers and their individual bits. 6.3.1.1 Interrupt Vector Base Register (IVBR) Address: 0x0120 IVB_ADDR[7:0] Reset Figure 6-2. Interrupt Vector Base Register (IVBR) Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 274: Functional Description
CPU to request the vector. In this case, the CPU will receive the highest priority vector and the system will process this interrupt request first, before the original interrupt request is processed. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 275: Reset Exception Requests
Spurious interrupt 16 bits vector address based D2D error interrupt on MCUs featuring a D2D initiator module, otherwise XIRQ pin interrupt D2D interrupt on MCUs featuring a D2D initiator module, otherwise IRQ pin interrupt MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 276: Initialization/Application Information
1. The capability of the XIRQ pin to wake-up the MCU with the X bit set may not be available if, for example, the XIRQ pin is shared with other peripheral modules on the device. Please refer to the Device section of the MCU reference manual for details. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 277 X interrupt request used for wake-up remains active at least until the system begins execution of the instruction following the WAI or STOP instruction; otherwise, wake-up may not occur. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 278 Interrupt Module (S12SINTV1) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 279: Chapter 7 Background Debug Module (S12Sbdmv1)
Clock switch removed from BDM (CLKSW bit removed from BDMSTS register) 7.1.1 Features The BDM includes these distinctive features: • Single-wire communication with host development system • Enhanced capability for allowing more flexibility in clock rates • SYNC command to determine communication rate MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 280: Modes Of Operation
BDM clocks will restart and BDM will have a soft reset (clearing the instruction register, any command in progress and disable the ACK function). The BDM is now ready to receive a new command. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 281: Block Diagram
(BDM soft reset) has occurred. Memory Map and Register Definition 7.3.1 Module Memory Map Table 7-2 shows the BDM memory map when BDM is active. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 282: Register Descriptions
CCR4 CCR3 CCR2 CCR1 CCR0 0x3_FF07 Reserved 0x3_FF08 BDMPPR BPAE BPP3 BPP2 BPP1 BPP0 = Unimplemented, Reserved = Implemented (do not alter) = Indeterminate = Always read zero Figure 7-2. BDM Register Summary MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 283 — All other bits, while writable via BDM hardware or standard BDM firmware write commands, should only be altered by the BDM hardware or standard firmware lookup table as part of BDM command execution. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 284 Register Global Address 0x3_FF06 CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0 Reset Special Single-Chip Mode All Other Modes Figure 7-4. BDM CCR Holding Register (BDMCCR) Read: All modes through BDM operation when not secured MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 285: Family Id Assignment
The read-only value is a unique family ID which is 0xC2 for devices with an HCS12S core. Functional Description The BDM receives and executes commands from a host via a single wire serial interface. There are two types of BDM commands: hardware and firmware commands. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 286: Security
BDM becomes active before or after execution of the next instruction. 1. BDM is enabled and active immediately out of special single-chip reset. 2. This method is provided by the S12S_DBG module. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 287: Bdm Hardware Commands
Enter background mode if BDM is enabled. If enabled, an ACK will be issued when the part enters active background mode. ACK_ENABLE None Enable Handshake. Issues an ACK pulse after the command is executed. ACK_DISABLE None Disable Handshake. This command does not issue an ACK pulse. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 288: Standard Bdm Firmware Commands
0x3_FF00–0x3_FFFF, and the CPU begins executing the standard BDM firmware. The standard BDM firmware watches for serial commands and executes them as they are received. The firmware commands are shown in Table 7-6. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 289: Bdm Command Structure
8-bit reads return 16-bits of data, only one byte of which contains valid data. If reading an even address, the valid data will appear in the MSB. If reading an odd address, the valid data will appear in the LSB. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 290 1. Target clock cycles are cycles measured using the target MCU’s serial clock rate. See Section 7.4.6, “BDM Serial Interface” Section 7.3.2.1, “BDM Status Register (BDMSTS)” for information on how serial clock rate is selected. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 291: Bdm Serial Interface
The target measures delays from this perceived start of the bit time while the host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 292 The host should sample the bit level about 10 target clock cycles after it started the bit time. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 293 Drive and Speedup Pulse Perceived Start of Bit Time BKGD Pin 10 Cycles 10 Cycles Earliest Start of Next Bit Host Samples BKGD Pin Figure 7-9. BDM Target-to-Host Serial Bit Timing (Logic 0) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 294: Serial Interface Hardware Handshake Protocol
If the CPU enters wait or stop prior to executing a hardware command, the ACK pulse will not be issued meaning that the BDM command was not executed. After entering wait or stop mode, the BDM command is no longer pending. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 295 After a certain time the host (not aware of stop or wait) should decide to abort any possible pending ACK pulse in order to be sure a new command can be issued. Therefore, the protocol provides a mechanism in which a command, and its corresponding ACK, can be aborted. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 296: Hardware Handshake Abort Procedure
The details about the short abort pulse are being provided only as a reference for the reader to better understand the BDM internal behavior. It is not recommended that this procedure be used in a real application. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 297 Electrical Conflict Speedup Pulse Host and Host Target Drive Drives SYNC to BKGD Pin To BKGD Pin Host SYNC Request Pulse BKGD Pin 16 Cycles Figure 7-13. ACK Pulse and SYNC Request Conflict MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 298 The TRACE1 command has the related ACK pulse issued when the CPU enters background active mode after one instruction of the application program is executed. The ACK pulse related to this command could be aborted using the SYNC command. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 299: Sync — Request Timed Reference Pulse
BDM firmware and the BDM is active and ready to receive a new command. If the TRACE1 command is issued again, the next user instruction will be executed. This facilitates stepping or tracing through the user code one instruction at a time. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 300: Serial Communication Time Out
This is the expected behavior if the handshake protocol is not enabled. In order to allow the data to be retrieved even with a large clock frequency mismatch (between BDM and CPU) when the hardware MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 301 The next negative edge in the BKGD pin, after a soft-reset has occurred, is considered by the target as the start of a new BDM command, or the start of a SYNC request pulse. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 302 Background Debug Module (S12SBDMV1) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 303: Chapter 8 S12S Debug Module (S12Sdbgv2)
DUG: Device User Guide, describing the features of the device into which the DBG is integrated WORD: 16-bit data entity Data Line: 20-bit data entity CPU: S12SCPU module DBG: S12SDBG module POR: Power On Reset MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 304: Overview
— Loop1: same as Normal but inhibits consecutive duplicate source address entries — Detail: address and data for all cycles except free cycles and opcode fetches are stored — Compressed Pure PC: all program counter addresses are stored MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 305: Modes Of Operation
CPU BUS MATCH CONTROL STATE LOGIC MATCH1 STATE SEQUENCER COMPARATOR B STATE MATCH2 COMPARATOR C TRACE CONTROL TRIGGER TRACE BUFFER READ TRACE DATA (DBG READ DATA BUS) Figure 8-1. Debug Module Block Diagram MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 306: External Signal Description
DBGACTL COMPE 0x0028 DBGBCTL COMPE 0x0028 DBGCCTL COMPE 0x0029 DBGXAH Bit 17 Bit 16 0x002A DBGXAM Bit 15 Bit 8 0x002B DBGXAL Bit 7 Bit 0 Figure 8-2. Quick Reference to DBG Registers MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 307: Register Descriptions
ARM = 1 preventing these bits from being written. These bits must be cleared using a second write if required. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 308 0x0027. See Table 8-4. Table 8-4. COMRV Encoding COMRV Visible Comparator Visible Register at 0x0027 Comparator A DBGSCR1 Comparator B DBGSCR2 Comparator C DBGSCR3 None DBGMFR 8.3.2.2 Debug Status Register (DBGSR) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 309 Table 8-6. SSF[2:0] — State Sequence Flag Bit Encoding SSF[2:0] Current State State0 (disarmed) State1 State2 State3 Final State 101,110,111 Reserved 8.3.2.3 Debug Trace Control Register (DBGTCR) Address: 0x0022 TSOURCE TRCMOD TALIGN Reset Figure 8-5. Debug Trace Control Register (DBGTCR) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 310 This register configures the comparators for range matching. Table 8-9. DBGC2 Field Descriptions Field Description 1–0 A and B Comparator Match Control — These bits determine the A and B comparator match mapping as ABCM[1:0] described in Table 8-10. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 311 The POR state is undefined. Other resets do not affect the trace buffer contents. 8.3.2.6 Debug Count Register (DBGCNT) Address: 0x0026 Reset — — — — — — — — = Unimplemented or Reserved Figure 8-8. Debug Count Register (DBGCNT) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 312 DBGC1 to blend in the required register. The COMRV = 11 value blends in the match flag register (DBGMFR). Table 8-14. State Control Register Access Encoding COMRV Visible State Control Register DBGSCR1 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 313 Match0 to State2..Match1 to State3 0101 Match1 to State3..Match0 to Final State 0110 Match0 to State2..Match2 to State3 0111 Either Match0 or Match1 to State2 1000 Reserved 1001 Match0 to State3 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 314 Description (Unspecified matches have no effect) 0000 Match0 to State1..Match2 to State3. 0001 Match1 to State3 0010 Match2 to State3 0011 Match1 to State3..Match0 Final State 0100 Match1 to State1..Match2 to State3. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 315 These bits select the targeted next state whilst in State3, based upon the match event. SC[3:0] Table 8-20. State3 — Sequencer Next State Selection SC[3:0] Description (Unspecified matches have no effect) 0000 Match0 to State1 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 316 Comparator A consists of 8 register bytes (3 address bus compare registers, two data bus compare registers, two data bus mask registers and a control register). Comparator B consists of four MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 317 Address: 0x0028 COMPE Reset = Unimplemented or Reserved Figure 8-14. Debug Comparator Control Register DBGBCTL (Comparator B) Address: 0x0028 COMPE Reset = Unimplemented or Reserved Figure 8-15. Debug Comparator Control Register DBGCCTL (Comparator C) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 318 RWE and RW on the comparison conditions. These bits are ignored if the corresponding TAG bit is set since the match occurs based on the tagged opcode reaching the execution stage of the instruction queue. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 319 [17:16] to a logic one or logic zero. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 320 [7:0] to a logic one or logic zero. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 321 A. Data bus comparisons are only performed if the TAG bit in DBGACTL is clear 0 Compare corresponding data bit to a logic zero 1 Compare corresponding data bit to a logic one MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 322: Functional Description
1 Compare corresponding data bit Functional Description This section provides a complete functional description of the DBG module. If the part is in secure mode, the DBG module can generate breakpoints but tracing is not possible. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 323: S12Sdbg Operation
The DBG contains three comparators, A, B and C. Each comparator compares the system address bus with the address stored in DBGXAH, DBGXAM, and DBGXAL. Furthermore, comparator A also compares the data buses to the data stored in DBGADH, DBGADL and allows masking of individual data bus bits. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 324 Comparator C offers only address and direction (R/W) comparison. The exact address is compared, thus with the comparator address register loaded with address (n) a word access of address (n–1) also accesses (n) but does not cause a match. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 325 Comparator A in the same way as described for Comparator C in Table 8-32. Table 8-34. Comparator A Matches When Accessing ADDR[n] DBGADHM, Access Comment DBGADLM DH=DBGADH, DL=DBGADL $0000 Byte No databus comparison Word MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 326 The corresponding DBGBCTL bits are ignored. The SZE and SZ control bits are ignored in range mode. The comparator A TAG bit is used to tag MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 327: Match Modes (Forced Or Tagged)
When the tagged instruction reaches the execution stage of the instruction queue a taghit is generated by the CPU. This can initiate a state sequencer transition. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 328: State Sequence Control
Further transitions between the states are then controlled by the state control registers and channel matches. From Final State the only permitted transition is back to the MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 329: Trace Buffer Operation
Using end alignment or when the tracing is initiated by writing to the TRIG bit whilst configured for begin alignment, tracing starts in the second cycle after the DBGC1 write cycle. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 330 COF has taken place. If an interrupt occurs simultaneously then the next instruction carried out is actually from the interrupt service routine. The instruction at the destination address of the original program flow gets executed after the interrupt service routine. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 331 This mode also features information bit storage to the trace buffer, for each address byte MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 332 Field 2 Field 1 Field 0 CINF1,ADRH1 ADRM1 ADRL1 Entry 1 DATAH1 DATAL1 Detail Mode CINF2,ADRH2 ADRM2 ADRL2 Entry 2 DATAH2 DATAL2 Entry 1 PCH1 PCM1 PCL1 Normal/Loop1 Modes Entry 2 PCH2 PCM2 PCL2 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 333 This bit has no meaning in Compressed Pure PC mode. 0 Non-Vector Destination Address 1 Vector Destination Address Program Counter bit 17— In Normal and Loop1 mode this bit corresponds to program counter bit 17. PC17 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 334 Each time that PC[17:6] differs from the previous base PC[17:6], then a new base address is stored. The base address zero value is the lowest address in the 64 address range The first line of the trace buffer always gets a base PC address, this applies also on rollover. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 335 In such cases the other contents of the trace buffer still contain valid tracing information. The case occurs when the reset assertion coincides with the trace buffer entry clock edge. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 336: Tagging
Table 8-42. Breakpoint Setup For CPU Breakpoints TALIGN DBGBRK Breakpoint Alignment Fill Trace Buffer until trigger then disarm (no breakpoints) Fill Trace Buffer until trigger, then breakpoint request occurs Start Trace Buffer at trigger (no breakpoints) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 337 BDM firmware code, checks the ENABLE and returns if ENABLE is not set. If not serviced by the monitor then the breakpoint is re-asserted when the BDM returns to normal CPU flow. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 338: Application Information
A trigger is generated if a given sequence of 3 code events is executed. Figure 8-27. Scenario 1 SCR2=0010 SCR3=0111 SCR1=0011 Final State State3 State2 State1 Scenario 1 is possible with S12SDBGV1 SCR encoding MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 339: Scenario 2
Trigger if a sequence of 2 events is carried out in an incorrect order. Event A must be followed by event B and event B must be followed by event A. 2 consecutive occurrences of event A without an intermediate MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 340 If no taghit points to final state then the lowest channel number has priority. Thus with the above encoding from State3, the CPU and DBG would break on a simultaneous M0/M2. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 341: Scenario 5
S12SDBGV1 SCR encoding because OR possibilities are very limited in the channel encoding. By adding OR forks as shown in red this scenario is possible. Figure 8-36. Scenario 7 SCR2=1100 SCR3=1101 SCR1=1101 Final State State3 State2 State1 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 342: Scenario 8
As shown up to 2 consecutive M2 events are allowed, whereby a reset to State1 is possible after either one or two M2 events. If an event M0 occurs following the second M2, before M1 resets to State1 then a trigger MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 343 Scenario 10b shows the case that after M2 then M1 must occur before M0. Starting from a particular point in code, event M2 must always be followed by M1 before M0. If after any M2, event M0 occurs before M1 then a trigger is generated. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 344 S12S Debug Module (S12SDBGV2) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 345: Chapter 9 Security (S12Xs9Secv2)
19 Apr 2007 corrected statement about Backdoor key access via BDM on XE, XF, XS Introduction This specification describes the function of the security mechanism in the MC9S12G-Family (9SEC). NOTE No security feature is absolutely secure. However, NXP’s strategy is to make reading or copying the FLASH and/or EEPROM difficult for unauthorized users.
Page 346: Securing The Microcontroller
SEC[1:0] = ‘10’. All other combinations put the device in a secured mode. The recommended value to put the device in secured state is the inverse of the unsecured state, i.e. SEC[1:0] = ‘01’. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 347: Operation Of The Secured Microcontroller
BDM hardware commands will be enabled, and the accessible memory space is restricted to the peripheral register area. This will allow the BDM to be used MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 348: Mc9S12G Family Reference Manual Rev.1.27 Nxp Semiconductors
(see Flash protection). Thus Flash protection is a useful means of preventing this method. The microcontroller will enter the unsecured state after the next reset following the programming of the security bits to the unsecured value. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 349: Complete Memory Erase (Special Modes)
Flash memory are erased, and this being the case, will enable all BDM commands, allowing the Flash options/security byte to be programmed to the unsecured value. The security bits SEC[1:0] in the Flash security register will indicate the unsecure state following the next reset. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 350 Security (S12XS9SECV2) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 351: Chapter 10 S12 Clock, Reset And Power Management Unit (S12Cpmu)
The Voltage regulator (IVREG) operates from the range 3.13V to 5.5V. It provides all the required chip internal voltages and voltage monitors. • The Phase Locked Loop (PLL) provides a highly accurate frequency multiplier with internal filter. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 352: Features
(A factory trim value is loaded from Flash Memory into the IRCTRIM register to turned off TC trimming after reset. Application can trim the TC if required by overwriting the IRCTRIM register). • Other features of the S12CPMU include • Clock monitor to detect loss of crystal MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 353: Modes Of Operation
– Program the reference divider (REFDIV[3:0] bits) to divide down oscillator frequency if necessary. – Enable the external oscillator (OSCE bit) – Wait for oscillator to start up (UPOSC=1) and PLL to lock (LOCK=1). • PLL Bypassed External (PBE) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 354 RTI counter halts. After wake-up from Full Stop Mode the Core Clock and Bus Clock are running on PLLCLK (PLLSEL=1). The COP runs on ACLK and RTI is running on IRCCLK (COPOSCSEL0=0, RTIOSCSEL=0). MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 355 1 or on exit from Full Stop Mode with OSCE bit already 1) the software must wait for a minimum time equivalent to the startup-time of the external oscillator t before entering Pseudo Stop Mode. UPOSC MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 356: S12Cpmu Block Diagram
RTI Interrupt ACLK RTIE COP time out COPCLK IRCCLK to Reset Watchdog Generator IRCCLK Real Time OSCCLK RTICLK Interrupt (RTI) OSCCLK CPMUCOP COPOSCSEL0 RTIOSCSEL CPMURTI UPOSC=0 clears Figure 10-1. Block diagram of S12CPMU MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 357: Signal Description
XOSCLCP is enabled, the MCU internal OSCCLK_LCP is derived from the EXTAL input frequency. If OSCE=0, the EXTAL pin is pulled down by an internal resistor of approximately 200 k and the XTAL pin is pulled down by an internal resistor of approximately 700 k. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 358: Vddr — Regulator Power Input Pin
An off-chip decoupling capacitor (100 nF...220 nF, X7R ceramic) between the combined supply pin pair can improve the quality of this supply. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 359: Vdd — Internal Regulator Output Supply (Core Logic)
LOCK UPOSC 0x0037 CPMUFLG RTIF PORF LVRF LOCKIF ILAF OSCIF 0x0038 CPMUINT RTIE LOCKIE OSCIE 0x0039 CPMUCLKS PLLSEL PSTP OSCSEL1 OSCSEL OSCSEL0 0x003A CPMUPLL = Unimplemented or Reserved Figure 10-3. CPMU Register Summary MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 360 MUTEST3 0x02F7 RESERVED CPMU 0x02F8 TCTRIM[4:0] IRCTRIM[9:8] IRCTRIMH CPMU 0x02F9 IRCTRIM[7:0] IRCTRIML OSCPINS_ 0x02FA CPMUOSC OSCE Reserved Reserved 0x02FB CPMUPROT PROT RESERVEDCP 0x02FC MUTEST2 = Unimplemented or Reserved Figure 10-3. CPMU Register Summary MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 361: Register Descriptions
10-1. Setting the VCOFRQ[1:0] bits incorrectly can result in a non functional PLL (no locking and/or insufficient stability). Table 10-1. VCO Clock Frequency Selection VCOCLK Frequency Ranges VCOFRQ[1:0] 32MHz <= f <= 48MHz 48MHz < f <= 50MHz Reserved MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 362 2MHz range. The bits can still be written but will have no effect on the PLL filter configuration. For OSCE=1, setting the REFFRQ[1:0] bits incorrectly can result in a non functional PLL (no locking and/or insufficient stability). MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 363 -------------- - If PLL is not locked (LOCK=0) f PLL f PLL If PLL is selected (PLLSEL=1) ------------ - f bus 10.3.2.4 S12CPMU Flags Register (CPMUFLG) This register provides S12CPMU status bits and flags. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 364 Illegal Address Reset Flag — ILAF is set to 1 when an illegal address reset occurs. Refer to MMC chapter for ILAF details. This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Illegal address reset has not occurred. 1 Illegal address reset has occurred. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 365 Oscillator Corrupt Interrupt Enable Bit OSCIE 0 Oscillator Corrupt interrupt requests are disabled. 1 Interrupt will be requested whenever OSCIF is set. 10.3.2.6 S12CPMU Clock Select Register (CPMUCLKS) This register controls S12CPMU clock selection. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 366 OSCCLK quality if OSCCLK is used as clock source for other clock domains: for instance core clock etc.). NOTE After writing CPMUCLKS register, it is strongly recommended to read back CPMUCLKS register to make sure that write of PLLSEL, RTIOSCSEL, COPOSCSEL0 and COPOSCSEL1 was successful. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 367 1 COP continues running during Pseudo Stop Mode if: PSTP=1, COPOSCSEL1=0 and COPOSCSEL0=1 Note: If PCE=0 or COPOSCSEL0=0 while COPOSCSEL1=0 then the COP is static during Stop Mode being active. The COP counter will not be reset. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 368 Figure 10-10. S12CPMU PLL Control Register (CPMUPLL) Read: Anytime Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has no effect. NOTE Write to this register clears the LOCK and UPOSC status bits. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 369 In Stop Mode with PSTP=1 (Pseudo Stop Mode) and RTIOSCSEL=1 the RTI continues to run, else the RTI counter halts in Stop Mode. 0x003B RTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0 Reset Figure 10-11. S12CPMU RTI Control Register (CPMURTI) Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 370 11x2 11x2 11x2 11x2 1010 (11) 12x2 12x2 12x2 12x2 12x2 12x2 12x2 1011 (12) 13x2 13x2 13x2 13x2 13x2 13x2 13x2 1100 (13) 14x2 14x2 14x2 14x2 14x2 14x2 14x2 1101 (14) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 371 75x10 150x10 300x10 750x10 1.5x10 3x10 1110 (15) 16x10 32x10 80x10 160x10 320x10 800x10 1.6x10 3.2x10 1111 (16) 10.3.2.9 S12CPMU COP Control Register (CPMUCOP) This register controls the COP (Computer Operating Properly) watchdog. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 372 2. Writing WCOP bit (anytime in Special Mode, once in Normal Mode) with WRTMASK = 0. 3. Changing RSBCK bit from “0” to “1”. In Special Mode, any write access to CPMUCOP register restarts the COP time-out period. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 373 4) Operation in Special Mode Table 10-13. COP Watchdog Rates if COPOSCSEL1=0 (default out of reset) COPCLK Cycles to Time-out (COPCLK is either IRCCLK or OSCCLK depending on the COPOSCSEL0 bit) COP disabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 374 10.3.2.11 Reserved Register CPMUTEST1 NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in Special Mode can alter the S12CPMU’s functionality. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 375 25% of the selected time-out period; writing any value in the first 75% of the selected period will cause a COP reset. 10.3.2.13 Low Voltage Control Register (CPMULVCTL) The CPMULVCTL register allows the configuration of the low-voltage detect features. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 376 The CPMUAPICTL register allows the configuration of the autonomous periodical interrupt features. 0x02F2 APICLK APIES APIEA APIFE APIE APIF Reset = Unimplemented or Reserved Figure 10-17. Autonomous Periodical Interrupt Control Register (CPMUAPICTL) Read: Anytime MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 377 0 has no effect. If enabled (APIE = 1), APIF causes an interrupt request. 0 API time-out has not yet occurred. 1 API time-out has occurred. Figure 10-18. Waveform selected on API_EXTCLK pin (APIEA=1, APIFE=1) API min. period / 2 APIES=0 API period APIES=1 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 378 Decreases period less than ACLKTR[2] ACLKTR[0] Decreases period less than ACLKTR[1] 10.3.2.16 Autonomous Periodical Interrupt Rate High and Low Register (CPMUAPIRH / CPMUAPIRL) The CPMUAPIRH and CPMUAPIRL registers allow the configuration of the autonomous periodical interrupt rate MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 379 API feature gets enabled (APIFE bit set) Table 10-20. Selectable Autonomous Periodical Interrupt Periods APICLK APIR[15:0] Selected Period 0000 0.2 ms 0001 0.4 ms 0002 0.6 ms 0003 0.8 ms MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 380 Writing to this register when in Special Mode can alter the S12CPMU’s functionality. 0x02F6 Reset = Unimplemented or Reserved Figure 10-22. Reserved Register (CPMUTEST3) Read: Anytime Write: Only in Special Mode MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 381 Figure 10-24. S12CPMU IRC1M Trim Low Register (CPMUIRCTRIML) Read: Anytime Write: Anytime if PROT=0 (CPMUPROT register). Else write has no effect NOTE Writes to these registers while PLLSEL=1 clears the LOCK and UPOSC status bits. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 382 Figure 10-25 shows the relationship between the trim bits and the resulting IRC1M frequency. IRC1M frequency (IRCCLK) IRCTRIM[9:6] 1.5MHz ..IRCTRIM[5:0] 1MHz 600KHz IRCTRIM[9:0] $000 $3FF Figure 10-25. IRC1M Frequency Trimming Diagram MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 383 TCTRIM[4:0] relative TC variation for relative TC variation 00000 0 (nominal TC of the IRC) 00001 -0.27% -0.5% 00010 -0.54% -0.9% 00011 -0.81% -1.3% 00100 -1.08% -1.7% 00101 -1.35% -2.0% 00110 -1.63% -2.2% MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 384 The values provided in Table 10-23 are typical values at ambient temperature which can vary from device to device. 10.3.2.19 S12CPMU Oscillator Register (CPMUOSC) This registers configures the external oscillator (XOSCLCP). MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 385 Do not alter these bits from their reset value. It is for Manufacturer use only and can change the PLL behavior. Reserved 10.3.2.20 S12CPMU Protection Register (CPMUPROT) This register protects the following clock configuration registers from accidental overwrite: MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 386 Writing to this register when in Special Mode can alter the S12CPMU’s functionality. 0x02FC Reset = Unimplemented or Reserved Figure 10-29. Reserved Register CPMUTEST2 Read: Anytime Write: Only in Special Mode MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 387: Functional Description
• Use lowest possible f ratio (SYNDIV value). • Use highest possible REFCLK frequency f Table 10-25. Examples of PLL Divider Settings REFDIV[3: POSTDIV REFFRQ[1:0] SYNDIV[5:0] VCOFRQ[1:0] [4:0] 1MHz 50MHz 12.5MHz 6.25MHz MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 388: Startup From Reset
Interrupt requests can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling the LOCK bit. 10.4.2 Startup from Reset An example of startup of clock system from Reset is given in Figure 10-30. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 389: Stop Mode Using Pllclk As Bus Clock
10.4.4 Full Stop Mode using Oscillator Clock as Bus Clock An example of what happens going into Full Stop Mode and exiting Full Stop Mode after an interrupt is shown in Figure 10-32. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 390: External Oscillator
PLLSEL automatically set when going into Full Stop Mode 10.4.5 External Oscillator 10.4.5.1 Enabling the External Oscillator An example of how to use the oscillator as Bus Clock is shown in Figure 10-33. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 391: System Clock Configurations
This mode can be entered from default mode PEI by performing the following steps: 1. Configure the PLL for desired bus frequency. 2. Enable the external oscillator (OSCE bit). 3. Wait for oscillator to start-up and the PLL being locked (LOCK = 1) and (UPOSC =1). MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 392 The PLLCLK is derived from the VCO clock (with its actual frequency) divided by four until the PLL locks again. • The OSCCLK provided to the MSCAN module is off. Application software needs to be prepared to deal with the impact of loosing the oscillator status at any time. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 393: Resets
Illegal Address Reset External pin RESET Clock Monitor Reset COP Reset Illegal Address Reset External pin RESET NOTE While System Reset is asserted the PLLCLK runs with the frequency VCORST MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 394 In Pseudo Stop Mode and Full Stop Mode with COPOSCSEL1=1 the COP continues to run. Table 10-28.gives an overview of the COP condition (run, static) in Stop Mode depending on legal configuration and status bit settings: MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 395: Power-On Reset (Por)
If LVR is deasserted the MCU is fully operational at the specified maximum speed. The LVR assert and deassert levels for the supply voltage VDDX are V and V and are LVRXA LVRXD specified in the device Reference Manual. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 396: Interrupts
When the OSCE bit is 0, then UPOSC stays 0. When OSCE = 1 the UPOSC bit is set after the LOCK bit is set. Upon detection of a status change (UPOSC) the OSCIF flag is set. Going into Full Stop Mode or disabling the oscillator can also cause a status change of UPOSC. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 397 It is possible to generate with the API a waveform at the external pin API_EXTCLK by setting APIFE and enabling the external access with setting APIEA. 1. For details please refer to “10.4.6 System Clock Configurations” MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 398: Initialization/Application Information
COP is written at the correct time (due to independent API interrupt request) but the wrong value is written (alternating sequence of $55 and $AA is no longer maintained) which causes a COP reset MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 399 S12 Clock, Reset and Power Management Unit (S12CPMU) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 400 S12 Clock, Reset and Power Management Unit (S12CPMU) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 401 S12 Clock, Reset and Power Management Unit (S12CPMU) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 402 S12 Clock, Reset and Power Management Unit (S12CPMU) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 403: Chapter 11 Analog-To-Digital Converter (Adc10B8Cv2)
(Section 11.4.2.1, “External Trigger Input). 11.1 Introduction The ADC10B8C is a 8-channel, 10-bit, multiplexed input successive approximation analog-to-digital converter. Refer to device electrical specifications for ATD accuracy. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 404: Features
The four additional trigger inputs can be chip external or internal. Refer to device specification for availability and connectivity. • Configurable location for channel wrap around (when converting multiple channels in a sequence). MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 405: Modes Of Operation
Wait mode. • Freeze Mode In Freeze Mode the ADC10B8C will either continue or finish or stop converting according to the FRZ1 and FRZ0 bits. This is useful for debugging and emulation. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 406: Block Diagram
ATD 0 ATD 1 ATD 2 VDDA ATD 3 ATD 4 VSSA ATD 5 Successive ATD 6 Approximation ATD 7 Register (SAR) and DAC Sample & Hold Comparator Analog Figure 11-1. ADC10B8C Block Diagram MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 407: Signal Description
WRAP0 0x0001 ATDCTL1 ETRIGSEL SRES1 SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 0x0002 ATDCTL2 AFFC Reserved ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE = Unimplemented or Reserved Figure 11-2. ADC10B8C Register Summary (Sheet 1 of 2) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 408 Section 11.3.2.12.1, “Left Justified Result Data (DJM=0)” 0x001E ATDDR7 Section 11.3.2.12.2, “Right Justified Result Data (DJM=1)” Unimple- 0x0020 - 0x002F mented = Unimplemented or Reserved Figure 11-2. ADC10B8C Register Summary (Sheet 2 of 2) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 409: Register Descriptions
Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing WRAP[3-0] multi-channel conversions. The coding is summarized in Table 11-2. Table 11-2. Multi-Channel Wrap Around Coding Multiple Channel Conversions (MULT = 1) WRAP3 WRAP2 WRAP1 WRAP0 Wraparound to AN0 after Converting Reserved MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 410 External Trigger Channel Select — These bits select one of the AD channels or one of the ETRIG3-0 inputs ETRIGCH[3:0] as source for the external trigger. The coding is summarized in Table 11-5. Table 11-4. A/D Resolution Coding SRES1 SRES0 A/D Resolution 8-bit data 10-bit data Reserved Reserved MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 411 Writes to this register will abort current conversion sequence. Module Base + 0x0002 AFFC Reserved ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE Reset = Unimplemented or Reserved Figure 11-5. ATD Control Register 2 (ATDCTL2) Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 412 1 For the conversions in a sequence for which automatic compare is enabled (CMPE[n]=1), an ATD Compare Interrupt will be requested whenever any of the respective CCF flags is set. Table 11-7. External Trigger Configurations ETRIGLE ETRIGP External Trigger Sensitivity Falling edge Rising edge Low level High level MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 413 Table 11-11. Leakage onto the storage node and comparator reference capacitors may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 414 0.008 0.006 0.004 0.003 0.002 0.000 Table 11-10. Conversion Sequence Length Coding Number of Conversions per Sequence Table 11-11. ATD Behavior in Freeze Mode (Breakpoint) FRZ1 FRZ0 Behavior in Freeze Mode Continue conversion MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 415 ATDCLK ------------------------------------ -    Refer to Device Specification for allowed frequency range of f ATDCLK Table 11-13. Sample Time Select Sample Time SMP2 SMP1 SMP0 in Number of ATD Clock Cycles MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 416 AN0 (after converting the channel defined by the Wrap Around Channel Select Bits WRAP3-0 in ATDCTL0). When starting with a channel number higher than the one defined by WRAP3-0 the first wrap around will be AN7 to AN0. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 417 Analog-to-Digital Converter (ADC10B8CV2) Table 11-15. Analog Input Channel Select Coding Analog Input Channel Internal_6, Internal_7 Internal_0 Internal_1 (VRH+VRL) / 2 Reserved Internal_2 Internal_3 Internal_4 Internal_5 Reserved MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 418 B) Write to ATDCTL0,1,2,3,4, ATDCMPE or ATDCMPHT (a conversion sequence is aborted) C) Write to ATDCTL5 (a new conversion sequence is started) 0 No overrun has occurred 1 Overrun condition exists (result register has been written while associated CCFx flag was still set) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 419 2) Write compare operator with CMPHT[n] in ATDCPMHT register CCF[n] in ATDSTAT2 register will flag individual success of any comparison. 0 No automatic compare 1 Automatic compare of results for conversion n of a sequence is enabled. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 420 1 If (CMPE[n]=0): Conversion number n has completed. Result is ready in ATDDRn. If (CMPE[n]=1): Compare for conversion result number n with compare value in ATDDRn, using compare operator CMPGT[n] is true. (No result available in ATDDRn) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 421 0 If result of conversion n is lower or same than compare value in ATDDRn, this is flagged in ATDSTAT2 1 If result of conversion n is higher than compare value in ATDDRn, this is flagged in ATDSTAT2 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 422 ATDDRn. Table 11-21. Conversion result mapping to ATDDRn ATDDRn conversion result mapping to resolution 8-bit data Result-Bit[11:4] = conversion result, Result-Bit[3:0]=0000 10-bit data Result-Bit[11:2] = conversion result, Result-Bit[1:0]=00 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 423 Compare is always done using all 12 bits of both the conversion result and the compare value in ATDDRn. Table 11-22. Conversion result mapping to ATDDRn ATDDRn conversion result mapping to resolution 8-bit data Result-Bit[7:0] = result, Result-Bit[11:8]=0000 10-bit data Result-Bit[9:0] = result, Result-Bit[11:10]=00 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 424: Functional Description
ATD module when a conversion is about to take place. The external trigger signal (out of reset ATD channel 7, configurable in ATDCTL1) is programmable to be edge MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 425 ATD input pin selected as analog input available to the A/D converter. The pad of the ATD input pin is always connected to the analog input channel of the analog mulitplexer. Each pad input signal is buffered to the digital port register. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 426: Resets
Table 11-24. ATD Interrupt Vectors Interrupt Source Local Enable Mask Sequence Complete Interrupt I bit ASCIE in ATDCTL2 Compare Interrupt I bit ACMPIE in ATDCTL2 Section 11.3.2, “Register Descriptions” for further details. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 427: Chapter 12 Analog-To-Digital Converter (Adc12B8Cv2)
(Section 12.4.2.1, “External Trigger Input). 12.1 Introduction The ADC12B8C is a 8-channel, 12-bit, multiplexed input successive approximation analog-to-digital converter. Refer to device electrical specifications for ATD accuracy. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 428: Features
The four additional trigger inputs can be chip external or internal. Refer to device specification for availability and connectivity. • Configurable location for channel wrap around (when converting multiple channels in a sequence). MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 429: Modes Of Operation
Wait mode. • Freeze Mode In Freeze Mode the ADC12B8C will either continue or finish or stop converting according to the FRZ1 and FRZ0 bits. This is useful for debugging and emulation. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 430: Block Diagram
ATD 0 ATD 1 ATD 2 VDDA ATD 3 ATD 4 VSSA ATD 5 Successive ATD 6 Approximation ATD 7 Register (SAR) and DAC Sample & Hold Comparator Analog Figure 12-1. ADC12B8C Block Diagram MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 431: Signal Description
WRAP0 0x0001 ATDCTL1 ETRIGSEL SRES1 SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 0x0002 ATDCTL2 AFFC Reserved ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE = Unimplemented or Reserved Figure 12-2. ADC12B8C Register Summary (Sheet 1 of 2) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 432 Section 12.3.2.12.1, “Left Justified Result Data (DJM=0)” 0x001E ATDDR7 Section 12.3.2.12.2, “Right Justified Result Data (DJM=1)” Unimple- 0x0020 - 0x002F mented = Unimplemented or Reserved Figure 12-2. ADC12B8C Register Summary (Sheet 2 of 2) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 433: Register Descriptions
Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing WRAP[3-0] multi-channel conversions. The coding is summarized in Table 12-2. Table 12-2. Multi-Channel Wrap Around Coding Multiple Channel Conversions (MULT = 1) WRAP3 WRAP2 WRAP1 WRAP0 Wraparound to AN0 after Converting Reserved MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 434 External Trigger Channel Select — These bits select one of the AD channels or one of the ETRIG3-0 inputs ETRIGCH[3:0] as source for the external trigger. The coding is summarized in Table 12-5. Table 12-4. A/D Resolution Coding SRES1 SRES0 A/D Resolution 8-bit data 10-bit data 12-bit data Reserved MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 435 Writes to this register will abort current conversion sequence. Module Base + 0x0002 AFFC Reserved ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE Reset = Unimplemented or Reserved Figure 12-5. ATD Control Register 2 (ATDCTL2) Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 436 1 For the conversions in a sequence for which automatic compare is enabled (CMPE[n]=1), an ATD Compare Interrupt will be requested whenever any of the respective CCF flags is set. Table 12-7. External Trigger Configurations ETRIGLE ETRIGP External Trigger Sensitivity Falling edge Rising edge Low level High level MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 437 Table 12-11. Leakage onto the storage node and comparator reference capacitors may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 438 VRH = 5.12 Volts (resolution=20mV) (resolution=5mV) (resolution=1.25mV) 5.120 Volts 1023 4095 0.022 0.020 0.018 0.016 0.014 0.012 0.010 0.008 0.006 0.004 0.003 0.002 0.000 Table 12-10. Conversion Sequence Length Coding Number of Conversions per Sequence MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 439 ATDCLK ------------------------------------ -    Refer to Device Specification for allowed frequency range of f ATDCLK Table 12-13. Sample Time Select Sample Time SMP2 SMP1 SMP0 in Number of ATD Clock Cycles MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 440 If the external trigger function is enabled (ETRIGE=1) setting this bit has no effect, thus the external trigger always starts a single conversion sequence. 0 Single conversion sequence 1 Continuous conversion sequences (scan mode) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 441 Select Bits WRAP3-0 in ATDCTL0). When starting with a channel number higher than the one defined by WRAP3-0 the first wrap around will be AN7 to AN0. Table 12-15. Analog Input Channel Select Coding Analog Input Channel MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 442 Analog-to-Digital Converter (ADC12B8CV2) Table 12-15. Analog Input Channel Select Coding Analog Input Channel Internal_6, Internal_7 Internal_0 Internal_1 (VRH+VRL) / 2 Reserved Internal_2 Internal_3 Internal_4 Internal_5 Reserved MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 443 B) Write to ATDCTL0,1,2,3,4, ATDCMPE or ATDCMPHT (a conversion sequence is aborted) C) Write to ATDCTL5 (a new conversion sequence is started) 0 No overrun has occurred 1 Overrun condition exists (result register has been written while associated CCFx flag was still set) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 444 2) Write compare operator with CMPHT[n] in ATDCPMHT register CCF[n] in ATDSTAT2 register will flag individual success of any comparison. 0 No automatic compare 1 Automatic compare of results for conversion n of a sequence is enabled. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 445 1 If (CMPE[n]=0): Conversion number n has completed. Result is ready in ATDDRn. If (CMPE[n]=1): Compare for conversion result number n with compare value in ATDDRn, using compare operator CMPGT[n] is true. (No result available in ATDDRn) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 446 0 If result of conversion n is lower or same than compare value in ATDDRn, this is flagged in ATDSTAT2 1 If result of conversion n is higher than compare value in ATDDRn, this is flagged in ATDSTAT2 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 447 ATDDRn. Table 12-21. Conversion result mapping to ATDDRn ATDDRn conversion result mapping to resolution 8-bit data Result-Bit[11:4] = conversion result, Result-Bit[3:0]=0000 10-bit data Result-Bit[11:2] = conversion result, Result-Bit[1:0]=00 12-bit data Result-Bit[11:0] = result MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 448 ATDDRn. Table 12-22. Conversion result mapping to ATDDRn ATDDRn conversion result mapping to resolution 8-bit data Result-Bit[7:0] = result, Result-Bit[11:8]=0000 10-bit data Result-Bit[9:0] = result, Result-Bit[11:10]=00 12-bit data Result-Bit[11:0] = result MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 449: Functional Description
ATD module when a conversion is about to take place. The external trigger signal (out of reset ATD channel 7, configurable in ATDCTL1) is programmable to be edge MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 450 ATD input pin selected as analog input available to the A/D converter. The pad of the ATD input pin is always connected to the analog input channel of the analog mulitplexer. Each pad input signal is buffered to the digital port register. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 451: Resets
Table 12-24. ATD Interrupt Vectors Interrupt Source Local Enable Mask Sequence Complete Interrupt I bit ASCIE in ATDCTL2 Compare Interrupt I bit ACMPIE in ATDCTL2 Section 12.3.2, “Register Descriptions” for further details. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 452 Analog-to-Digital Converter (ADC12B8CV2) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 453: Chapter 13 Analog-To-Digital Converter (Adc10B12Cv2)
Removed IP name in block diagram Figure 13-1 Added user information to avoid maybe false external trigger V02.11 02 Oct 2012 02 Oct 2012 events when enabling the external trigger mode (Section 13.4.2.1, “External Trigger Input). MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 454: Introduction
The four additional trigger inputs can be chip external or internal. Refer to device specification for availability and connectivity. • Configurable location for channel wrap around (when converting multiple channels in a sequence). MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 455: Modes Of Operation
Wait mode. • Freeze Mode In Freeze Mode the ADC10B12C will either continue or finish or stop converting according to the FRZ1 and FRZ0 bits. This is useful for debugging and emulation. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 456: Block Diagram
VSSA ATD 5 Successive ATD 6 Approximation ATD 7 ATD 8 Register (SAR) ATD 9 and DAC ATD 10 ATD 11 AN11 AN10 Sample & Hold Comparator Analog Figure 13-1. ADC10B12C Block Diagram MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 457: Signal Description
WRAP0 0x0001 ATDCTL1 ETRIGSEL SRES1 SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 0x0002 ATDCTL2 AFFC Reserved ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE = Unimplemented or Reserved Figure 13-2. ADC10B12C Register Summary (Sheet 1 of 3) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 458 Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)” Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)” 0x0022 ATDDR9 Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)” = Unimplemented or Reserved Figure 13-2. ADC10B12C Register Summary (Sheet 2 of 3) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 459 Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)” 0x0026 ATDDR11 Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)” Unimple- 0x0028 - 0x002F mented = Unimplemented or Reserved Figure 13-2. ADC10B12C Register Summary (Sheet 3 of 3) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 460: Register Descriptions
The coding is summarized in Table 13-2. Table 13-2. Multi-Channel Wrap Around Coding Multiple Channel Conversions (MULT = 1) WRAP3 WRAP2 WRAP1 WRAP0 Wraparound to AN0 after Converting Reserved AN10 AN11 AN11 AN11 AN11 AN11 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 461 External Trigger Channel Select — These bits select one of the AD channels or one of the ETRIG3-0 inputs ETRIGCH[3:0] as source for the external trigger. The coding is summarized in Table 13-5. Table 13-4. A/D Resolution Coding SRES1 SRES0 A/D Resolution 8-bit data 10-bit data Reserved Reserved MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 462 Writes to this register will abort current conversion sequence. Module Base + 0x0002 AFFC Reserved ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE Reset = Unimplemented or Reserved Figure 13-5. ATD Control Register 2 (ATDCTL2) Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 463 1 For the conversions in a sequence for which automatic compare is enabled (CMPE[n]=1), an ATD Compare Interrupt will be requested whenever any of the respective CCF flags is set. Table 13-7. External Trigger Configurations ETRIGLE ETRIGP External Trigger Sensitivity Falling edge Rising edge Low level High level MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 464 Table 13-11. Leakage onto the storage node and comparator reference capacitors may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 465 0.008 0.006 0.004 0.003 0.002 0.000 Table 13-10. Conversion Sequence Length Coding Number of Conversions per Sequence Table 13-11. ATD Behavior in Freeze Mode (Breakpoint) FRZ1 FRZ0 Behavior in Freeze Mode Continue conversion MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 466 ATDCLK ------------------------------------ -    Refer to Device Specification for allowed frequency range of f ATDCLK Table 13-13. Sample Time Select Sample Time SMP2 SMP1 SMP0 in Number of ATD Clock Cycles MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 467 AN0 (after converting the channel defined by the Wrap Around Channel Select Bits WRAP3-0 in ATDCTL0). When starting with a channel number higher than the one defined by WRAP3-0 the first wrap around will be AN11 to AN0. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 468 Analog-to-Digital Converter (ADC10B12CV2) Table 13-15. Analog Input Channel Select Coding Analog Input Channel AN10 AN11 AN11 AN11 AN11 AN11 Internal_6, Internal_7 Internal_0 Internal_1 (VRH+VRL) / 2 Reserved Internal_2 Internal_3 Internal_4 Internal_5 Reserved MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 469 B) Write to ATDCTL0,1,2,3,4, ATDCMPE or ATDCMPHT (a conversion sequence is aborted) C) Write to ATDCTL5 (a new conversion sequence is started) 0 No overrun has occurred 1 Overrun condition exists (result register has been written while associated CCFx flag was still set) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 470 2) Write compare operator with CMPHT[n] in ATDCPMHT register CCF[n] in ATDSTAT2 register will flag individual success of any comparison. 0 No automatic compare 1 Automatic compare of results for conversion n of a sequence is enabled. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 471 1 If (CMPE[n]=0): Conversion number n has completed. Result is ready in ATDDRn. If (CMPE[n]=1): Compare for conversion result number n with compare value in ATDDRn, using compare operator CMPGT[n] is true. (No result available in ATDDRn) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 472 0 If result of conversion n is lower or same than compare value in ATDDRn, this is flagged in ATDSTAT2 1 If result of conversion n is higher than compare value in ATDDRn, this is flagged in ATDSTAT2 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 473 ATDDRn. Table 13-21. Conversion result mapping to ATDDRn ATDDRn conversion result mapping to resolution 8-bit data Result-Bit[11:4] = conversion result, Result-Bit[3:0]=0000 10-bit data Result-Bit[11:2] = conversion result, Result-Bit[1:0]=00 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 474 ATDDRn. Table 13-22. Conversion result mapping to ATDDRn ATDDRn conversion result mapping to resolution 8-bit data Result-Bit[11:8]=0000, Result-Bit[7:0] = conversion result 10-bit data Result-Bit[11:10]=00, Result-Bit[9:0] = conversion result MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 475: Functional Description
ATD module when a conversions is about to take place. The external trigger signal (out of reset ATD channel 11, configurable in ATDCTL1) is programmable to be MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 476 This buffer can be turned on or off with the ATDDIEN register for each ATD input pin. This is important so that the buffer does not draw excess current when an ATD input pin is selected as analog input to the ADC10B12C. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 477: Resets
Table 13-24. ATD Interrupt Vectors Interrupt Source Local Enable Mask Sequence Complete Interrupt I bit ASCIE in ATDCTL2 Compare Interrupt I bit ACMPIE in ATDCTL2 Section 13.3.2, “Register Descriptions” for further details. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 478 Analog-to-Digital Converter (ADC10B12CV2) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 479: Chapter 14 Analog-To-Digital Converter (Adc12B12Cv2)
Removed IP name in block diagram Figure 14-1 Added user information to avoid maybe false external trigger V02.11 02 Oct 2012 02 Oct 2012 events when enabling the external trigger mode (Section 14.4.2.1, “External Trigger Input). MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 480: Introduction
The four additional trigger inputs can be chip external or internal. Refer to device specification for availability and connectivity. • Configurable location for channel wrap around (when converting multiple channels in a sequence). MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 481: Modes Of Operation
Wait mode. • Freeze Mode In Freeze Mode the ADC12B12C will either continue or finish or stop converting according to the FRZ1 and FRZ0 bits. This is useful for debugging and emulation. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 482: Block Diagram
VSSA ATD 5 Successive ATD 6 Approximation ATD 7 ATD 8 Register (SAR) ATD 9 and DAC ATD 10 ATD 11 AN11 AN10 Sample & Hold Comparator Analog Figure 14-1. ADC12B12C Block Diagram MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 483: Signal Description
WRAP0 0x0001 ATDCTL1 ETRIGSEL SRES1 SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 0x0002 ATDCTL2 AFFC Reserved ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE = Unimplemented or Reserved Figure 14-2. ADC12B12C Register Summary (Sheet 1 of 3) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 484 Section 14.3.2.12.2, “Right Justified Result Data (DJM=1)” Section 14.3.2.12.1, “Left Justified Result Data (DJM=0)” 0x0022 ATDDR9 Section 14.3.2.12.2, “Right Justified Result Data (DJM=1)” = Unimplemented or Reserved Figure 14-2. ADC12B12C Register Summary (Sheet 2 of 3) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 485 Section 14.3.2.12.1, “Left Justified Result Data (DJM=0)” 0x0026 ATDDR11 Section 14.3.2.12.2, “Right Justified Result Data (DJM=1)” Unimple- 0x0028 - 0x002F mented = Unimplemented or Reserved Figure 14-2. ADC12B12C Register Summary (Sheet 3 of 3) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 486: Register Descriptions
The coding is summarized in Table 14-2. Table 14-2. Multi-Channel Wrap Around Coding Multiple Channel Conversions (MULT = 1) WRAP3 WRAP2 WRAP1 WRAP0 Wraparound to AN0 after Converting Reserved AN10 AN11 AN11 AN11 AN11 AN11 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 487 External Trigger Channel Select — These bits select one of the AD channels or one of the ETRIG3-0 inputs ETRIGCH[3:0] as source for the external trigger. The coding is summarized in Table 14-5. Table 14-4. A/D Resolution Coding SRES1 SRES0 A/D Resolution 8-bit data 10-bit data 12-bit data Reserved MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 488 Writes to this register will abort current conversion sequence. Module Base + 0x0002 AFFC Reserved ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE Reset = Unimplemented or Reserved Figure 14-5. ATD Control Register 2 (ATDCTL2) Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 489 1 For the conversions in a sequence for which automatic compare is enabled (CMPE[n]=1), an ATD Compare Interrupt will be requested whenever any of the respective CCF flags is set. Table 14-7. External Trigger Configurations ETRIGLE ETRIGP External Trigger Sensitivity Falling edge Rising edge Low level High level MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 490 Table 14-11. Leakage onto the storage node and comparator reference capacitors may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 491 VRH = 5.12 Volts (resolution=20mV) (resolution=5mV) (resolution=1.25mV) 5.120 Volts 1023 4095 0.022 0.020 0.018 0.016 0.014 0.012 0.010 0.008 0.006 0.004 0.003 0.002 0.000 Table 14-10. Conversion Sequence Length Coding Number of Conversions per Sequence MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 492 ATDCLK ------------------------------------ -    Refer to Device Specification for allowed frequency range of f ATDCLK Table 14-13. Sample Time Select Sample Time SMP2 SMP1 SMP0 in Number of ATD Clock Cycles MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 493 If the external trigger function is enabled (ETRIGE=1) setting this bit has no effect, thus the external trigger always starts a single conversion sequence. 0 Single conversion sequence 1 Continuous conversion sequences (scan mode) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 494 Select Bits WRAP3-0 in ATDCTL0). When starting with a channel number higher than the one defined by WRAP3-0 the first wrap around will be AN11 to AN0. Table 14-15. Analog Input Channel Select Coding Analog Input Channel AN10 AN11 AN11 AN11 AN11 AN11 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 495 Analog-to-Digital Converter (ADC12B12CV2) Table 14-15. Analog Input Channel Select Coding Analog Input Channel Internal_6, Internal_7 Internal_0 Internal_1 (VRH+VRL) / 2 Reserved Internal_2 Internal_3 Internal_4 Internal_5 Reserved MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 496 B) Write to ATDCTL0,1,2,3,4, ATDCMPE or ATDCMPHT (a conversion sequence is aborted) C) Write to ATDCTL5 (a new conversion sequence is started) 0 No overrun has occurred 1 Overrun condition exists (result register has been written while associated CCFx flag was still set) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 497 2) Write compare operator with CMPHT[n] in ATDCPMHT register CCF[n] in ATDSTAT2 register will flag individual success of any comparison. 0 No automatic compare 1 Automatic compare of results for conversion n of a sequence is enabled. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 498 1 If (CMPE[n]=0): Conversion number n has completed. Result is ready in ATDDRn. If (CMPE[n]=1): Compare for conversion result number n with compare value in ATDDRn, using compare operator CMPGT[n] is true. (No result available in ATDDRn) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 499 0 If result of conversion n is lower or same than compare value in ATDDRn, this is flagged in ATDSTAT2 1 If result of conversion n is higher than compare value in ATDDRn, this is flagged in ATDSTAT2 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 500 ATDDRn. Table 14-21. Conversion result mapping to ATDDRn ATDDRn conversion result mapping to resolution 8-bit data Result-Bit[11:4] = conversion result, Result-Bit[3:0]=0000 10-bit data Result-Bit[11:2] = conversion result, Result-Bit[1:0]=00 12-bit data Result-Bit[11:0] = result MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 501 ATDDRn. Table 14-22. Conversion result mapping to ATDDRn ATDDRn conversion result mapping to resolution 8-bit data Result-Bit[11:8]=0000, Result-Bit[7:0] = conversion result 10-bit data Result-Bit[11:10]=00, Result-Bit[9:0] = conversion result 12-bit data Result-Bit[11:0] = result MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 502: Functional Description
ATD module when a conversions is about to take place. The external trigger signal (out of reset ATD channel 11, configurable in ATDCTL1) is programmable to be MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 503 This buffer can be turned on or off with the ATDDIEN register for each ATD input pin. This is important so that the buffer does not draw excess current when an ATD input pin is selected as analog input to the ADC12B12C. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 504: Resets
Table 14-24. ATD Interrupt Vectors Interrupt Source Local Enable Mask Sequence Complete Interrupt I bit ASCIE in ATDCTL2 Compare Interrupt I bit ACMPIE in ATDCTL2 Section 14.3.2, “Register Descriptions” for further details. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 505: Chapter 15 Analog-To-Digital Converter (Adc10B16Cv2)
Removed IP name in block diagram Figure 15-1 Added user information to avoid maybe false external trigger V02.12 02 Oct 2012 02 Oct 2012 events when enabling the external trigger mode (Section 15.4.2.1, “External Trigger Input). MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 506: Introduction
The four additional trigger inputs can be chip external or internal. Refer to device specification for availability and connectivity. • Configurable location for channel wrap around (when converting multiple channels in a sequence). MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 507: Modes Of Operation
Wait mode. • Freeze Mode In Freeze Mode the ADC10B16C will either continue or finish or stop converting according to the FRZ1 and FRZ0 bits. This is useful for debugging and emulation. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 508: Block Diagram
Register (SAR) ATD 9 and DAC ATD 10 ATD 11 AN15 ATD 12 ATD 13 AN14 ATD 14 AN13 ATD 15 AN12 AN11 Sample & Hold AN10 Comparator Analog Figure 15-1. ADC10B16C Block Diagram MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 509: Signal Description
WRAP0 0x0001 ATDCTL1 ETRIGSEL SRES1 SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 0x0002 ATDCTL2 AFFC Reserved ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE = Unimplemented or Reserved Figure 15-2. ADC10B16C Register Summary (Sheet 1 of 3) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 510 Section 15.3.2.12.2, “Right Justified Result Data (DJM=1)” Section 15.3.2.12.1, “Left Justified Result Data (DJM=0)” 0x0022 ATDDR9 Section 15.3.2.12.2, “Right Justified Result Data (DJM=1)” = Unimplemented or Reserved Figure 15-2. ADC10B16C Register Summary (Sheet 2 of 3) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 511 Section 15.3.2.12.2, “Right Justified Result Data (DJM=1)” Section 15.3.2.12.1, “Left Justified Result Data (DJM=0)” 0x002E ATDDR15 Section 15.3.2.12.2, “Right Justified Result Data (DJM=1)” = Unimplemented or Reserved Figure 15-2. ADC10B16C Register Summary (Sheet 3 of 3) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 512: Register Descriptions
The coding is summarized in Table 15-2. Table 15-2. Multi-Channel Wrap Around Coding Multiple Channel Conversions (MULT = 1) WRAP3 WRAP2 WRAP1 WRAP0 Wraparound to AN0 after Converting Reserved AN10 AN11 AN12 AN13 AN14 AN15 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 513 External Trigger Channel Select — These bits select one of the AD channels or one of the ETRIG3-0 inputs ETRIGCH[3:0] as source for the external trigger. The coding is summarized in Table 15-5. Table 15-4. A/D Resolution Coding SRES1 SRES0 A/D Resolution 8-bit data 10-bit data Reserved Reserved MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 514 Writes to this register will abort current conversion sequence. Module Base + 0x0002 AFFC Reserved ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE Reset = Unimplemented or Reserved Figure 15-5. ATD Control Register 2 (ATDCTL2) Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 515 1 For the conversions in a sequence for which automatic compare is enabled (CMPE[n]=1), an ATD Compare Interrupt will be requested whenever any of the respective CCF flags is set. Table 15-7. External Trigger Configurations ETRIGLE ETRIGP External Trigger Sensitivity Falling edge Rising edge Low level High level MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 516 Table 15-11. Leakage onto the storage node and comparator reference capacitors may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 517 0.008 0.006 0.004 0.003 0.002 0.000 Table 15-10. Conversion Sequence Length Coding Number of Conversions per Sequence Table 15-11. ATD Behavior in Freeze Mode (Breakpoint) FRZ1 FRZ0 Behavior in Freeze Mode Continue conversion MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 518 ATDCLK ------------------------------------ -    Refer to Device Specification for allowed frequency range of f ATDCLK Table 15-13. Sample Time Select Sample Time SMP2 SMP1 SMP0 in Number of ATD Clock Cycles MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 519 AN0 (after converting the channel defined by the Wrap Around Channel Select Bits WRAP3-0 in ATDCTL0). When starting with a channel number higher than the one defined by WRAP3-0 the first wrap around will be AN16 to AN0. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 520 Analog-to-Digital Converter (ADC10B16CV2) Table 15-15. Analog Input Channel Select Coding Analog Input Channel AN10 AN11 AN12 AN13 AN14 AN15 Internal_6, Internal_7 Internal_0 Internal_1 (VRH+VRL) / 2 Reserved Internal_2 Internal_3 Internal_4 Internal_5 Reserved MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 521 B) Write to ATDCTL0,1,2,3,4, ATDCMPE or ATDCMPHT (a conversion sequence is aborted) C) Write to ATDCTL5 (a new conversion sequence is started) 0 No overrun has occurred 1 Overrun condition exists (result register has been written while associated CCFx flag was still set) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 522 2) Write compare operator with CMPHT[n] in ATDCPMHT register CCF[n] in ATDSTAT2 register will flag individual success of any comparison. 0 No automatic compare 1 Automatic compare of results for conversion n of a sequence is enabled. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 523 1 If (CMPE[n]=0): Conversion number n has completed. Result is ready in ATDDRn. If (CMPE[n]=1): Compare for conversion result number n with compare value in ATDDRn, using compare operator CMPGT[n] is true. (No result available in ATDDRn) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 524 0 If result of conversion n is lower or same than compare value in ATDDRn, this is flagged in ATDSTAT2 1 If result of conversion n is higher than compare value in ATDDRn, this is flagged in ATDSTAT2 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 525 ATDDRn. Table 15-21. Conversion result mapping to ATDDRn ATDDRn conversion result mapping to resolution 8-bit data Result-Bit[11:4] = conversion result, Result-Bit[3:0]=0000 10-bit data Result-Bit[11:2] = conversion result, Result-Bit[1:0]=00 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 526 Compare is always done using all 12 bits of both the conversion result and the compare value in ATDDRn. Table 15-22. Conversion result mapping to ATDDRn ATDDRn conversion result mapping to resolution 8-bit data Result-Bit[7:0] = result, Result-Bit[11:8]=0000 10-bit data Result-Bit[9:0] = result, Result-Bit[11:10]=00 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 527: Functional Description
ATD module when a conversion is about to take place. The external trigger signal (out of reset ATD channel 15, configurable in ATDCTL1) is programmable to be MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 528 This buffer can be turned on or off with the ATDDIEN register for each ATD input pin. This is important so that the buffer does not draw excess current when an ATD input pin is selected as analog input to the ADC10B16C. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 529: Resets
Table 15-24. ATD Interrupt Vectors Interrupt Source Local Enable Mask Sequence Complete Interrupt I bit ASCIE in ATDCTL2 Compare Interrupt I bit ACMPIE in ATDCTL2 Section 15.3.2, “Register Descriptions” for further details. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 530 Analog-to-Digital Converter (ADC10B16CV2) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 531: Chapter 16 Analog-To-Digital Converter (Adc12B16Cv2)
Removed IP name in block diagram Figure 16-1 Added user information to avoid maybe false external trigger V02.12 02 Oct 2012 02 Oct 2012 events when enabling the external trigger mode (Section 16.4.2.1, “External Trigger Input). MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 532: Introduction
The four additional trigger inputs can be chip external or internal. Refer to device specification for availability and connectivity. • Configurable location for channel wrap around (when converting multiple channels in a sequence). MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 533: Modes Of Operation
Wait mode. • Freeze Mode In Freeze Mode the ADC12B16C will either continue or finish or stop converting according to the FRZ1 and FRZ0 bits. This is useful for debugging and emulation. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 534: Block Diagram
Register (SAR) ATD 9 and DAC ATD 10 ATD 11 AN15 ATD 12 ATD 13 AN14 ATD 14 AN13 ATD 15 AN12 AN11 Sample & Hold AN10 Comparator Analog Figure 16-1. ADC12B16C Block Diagram MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 535: Signal Description
WRAP0 0x0001 ATDCTL1 ETRIGSEL SRES1 SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 0x0002 ATDCTL2 AFFC Reserved ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE = Unimplemented or Reserved Figure 16-2. ADC12B16C Register Summary (Sheet 1 of 3) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 536 Section 16.3.2.12.2, “Right Justified Result Data (DJM=1)” Section 16.3.2.12.1, “Left Justified Result Data (DJM=0)” 0x0022 ATDDR9 Section 16.3.2.12.2, “Right Justified Result Data (DJM=1)” = Unimplemented or Reserved Figure 16-2. ADC12B16C Register Summary (Sheet 2 of 3) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 537 Section 16.3.2.12.2, “Right Justified Result Data (DJM=1)” Section 16.3.2.12.1, “Left Justified Result Data (DJM=0)” 0x002E ATDDR15 Section 16.3.2.12.2, “Right Justified Result Data (DJM=1)” = Unimplemented or Reserved Figure 16-2. ADC12B16C Register Summary (Sheet 3 of 3) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 538: Register Descriptions
The coding is summarized in Table 16-2. Table 16-2. Multi-Channel Wrap Around Coding Multiple Channel Conversions (MULT = 1) WRAP3 WRAP2 WRAP1 WRAP0 Wraparound to AN0 after Converting Reserved AN10 AN11 AN12 AN13 AN14 AN15 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 539 External Trigger Channel Select — These bits select one of the AD channels or one of the ETRIG3-0 inputs ETRIGCH[3:0] as source for the external trigger. The coding is summarized in Table 16-5. Table 16-4. A/D Resolution Coding SRES1 SRES0 A/D Resolution 8-bit data 10-bit data 12-bit data Reserved MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 540 Writes to this register will abort current conversion sequence. Module Base + 0x0002 AFFC Reserved ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE Reset = Unimplemented or Reserved Figure 16-5. ATD Control Register 2 (ATDCTL2) Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 541 1 For the conversions in a sequence for which automatic compare is enabled (CMPE[n]=1), an ATD Compare Interrupt will be requested whenever any of the respective CCF flags is set. Table 16-7. External Trigger Configurations ETRIGLE ETRIGP External Trigger Sensitivity Falling edge Rising edge Low level High level MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 542 Table 16-11. Leakage onto the storage node and comparator reference capacitors may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 543 VRH = 5.12 Volts (resolution=20mV) (resolution=5mV) (resolution=1.25mV) 5.120 Volts 1023 4095 0.022 0.020 0.018 0.016 0.014 0.012 0.010 0.008 0.006 0.004 0.003 0.002 0.000 Table 16-10. Conversion Sequence Length Coding Number of Conversions per Sequence MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 544 ATDCLK ------------------------------------ -    Refer to Device Specification for allowed frequency range of f ATDCLK Table 16-13. Sample Time Select Sample Time SMP2 SMP1 SMP0 in Number of ATD Clock Cycles MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 545 If the external trigger function is enabled (ETRIGE=1) setting this bit has no effect, thus the external trigger always starts a single conversion sequence. 0 Single conversion sequence 1 Continuous conversion sequences (scan mode) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 546 Select Bits WRAP3-0 in ATDCTL0). When starting with a channel number higher than the one defined by WRAP3-0 the first wrap around will be AN16 to AN0. Table 16-15. Analog Input Channel Select Coding Analog Input Channel AN10 AN11 AN12 AN13 AN14 AN15 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 547 Analog-to-Digital Converter (ADC12B16CV2) Table 16-15. Analog Input Channel Select Coding Analog Input Channel Internal_6, Internal_7 Internal_0 Internal_1 (VRH+VRL) / 2 Reserved Internal_2 Internal_3 Internal_4 Internal_5 Reserved MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 548 B) Write to ATDCTL0,1,2,3,4, ATDCMPE or ATDCMPHT (a conversion sequence is aborted) C) Write to ATDCTL5 (a new conversion sequence is started) 0 No overrun has occurred 1 Overrun condition exists (result register has been written while associated CCFx flag was still set) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 549 2) Write compare operator with CMPHT[n] in ATDCPMHT register CCF[n] in ATDSTAT2 register will flag individual success of any comparison. 0 No automatic compare 1 Automatic compare of results for conversion n of a sequence is enabled. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 550 1 If (CMPE[n]=0): Conversion number n has completed. Result is ready in ATDDRn. If (CMPE[n]=1): Compare for conversion result number n with compare value in ATDDRn, using compare operator CMPGT[n] is true. (No result available in ATDDRn) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 551 0 If result of conversion n is lower or same than compare value in ATDDRn, this is flagged in ATDSTAT2 1 If result of conversion n is higher than compare value in ATDDRn, this is flagged in ATDSTAT2 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 552 ATDDRn. Table 16-21. Conversion result mapping to ATDDRn ATDDRn conversion result mapping to resolution 8-bit data Result-Bit[11:4] = conversion result, Result-Bit[3:0]=0000 10-bit data Result-Bit[11:2] = conversion result, Result-Bit[1:0]=00 12-bit data Result-Bit[11:0] = result MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 553 ATDDRn. Table 16-22. Conversion result mapping to ATDDRn ATDDRn conversion result mapping to resolution 8-bit data Result-Bit[7:0] = result, Result-Bit[11:8]=0000 10-bit data Result-Bit[9:0] = result, Result-Bit[11:10]=00 12-bit data Result-Bit[11:0] = result MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 554: Functional Description
ATD module when a conversion is about to take place. The external trigger signal (out of reset ATD channel 15, configurable in ATDCTL1) is programmable to be MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 555 This buffer can be turned on or off with the ATDDIEN register for each ATD input pin. This is important so that the buffer does not draw excess current when an ATD input pin is selected as analog input to the ADC12B16C. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 556: Resets
Table 16-24. ATD Interrupt Vectors Interrupt Source Local Enable Mask Sequence Complete Interrupt I bit ASCIE in ATDCTL2 Compare Interrupt I bit ACMPIE in ATDCTL2 Section 16.3.2, “Register Descriptions” for further details. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 557: Chapter 17 Digital Analog Converter (Dac_8B5V)
The DAC_8B5V module is a digital to analog converter. The converter works with a resolution of 8 bit and generates an output voltage between VRL and VRH. The module consists of configuration registers and two analog functional units, a DAC resistor network and an operational amplifier. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 558: Features
The content of the configuration registers is unchanged. NOTE After enabling and after return from CPU stop mode, the DAC_8B5V module needs a settling time to get fully operational, see Settling time specification of dac_8b5V_analog_ll18. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 559: Block Diagram
DACM[2:0]. 17.3.3 AMPP Input Pin This analog input pin is used as input signal for the operational amplifier positive input pin, if the according mode is selected, see register bit DACM[2:0]. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 560: Ampm Input Pin
DACCTL DRIVE DACM[2:0] 0x0001 Reserved 0x0002 DACVOL VOLTAGE[7:0] 0x0003 - 0x0006 Reserved 0x0007 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x0007 DACDEBUG BUF_EN DAC_EN = Unimplemented Figure 17-2. DAC_8B5V Register Summaryfv_dac_8b5v_RESERVED MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 561: Register Descriptions
Mode Select — These bits define the mode of the DAC. A write access with an unsupported mode will be ignored. DACM[2:0] 000 Off 001 Operational Amplifier 100 Unbuffered DAC 101 Unbuffered DAC with Operational Amplifier 111 Buffered DAC other Reserved MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 562: Functional Description
The DAC resistor network and the operational amplifier can be used together or stand alone. Following modes are supported: Table 17-5. DAC Modes of Operation Description Submodules Output DACM[2:0] DAC resistor Operational DACU network Amplifier disabled disabled disconnected disconnected MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 563: Mode "Off
AMP, AMPP and AMPM are available on the pins. The DAC resistor network output is disconnected from the DACU pin. The connection between the amplifier output and the negative amplifier input is open. For decoding of the control signals see Table 17-7. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 564: Mode "Unbuffered Dac
The DAC generates an analog output voltage inside the range from VRL to VRH with a resolution (VRH-VRL) / 256, see equation below: analog output voltage = VOLTAGE[7:0] x (VRH-VRL) / 256 +VRL Eqn. 17-2 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 565 VRL = 0.0 V and VRH = 5.0 V. Table 17-8. Analog output voltage calculation max. min. voltage Resolution Equation voltage 0.5V 4.484V 15.625mV VOLTAGE[7:0] x (4.0V) / 256) + 0.5V 0.0V 4.980V 19.531mV VOLTAGE[7:0] x (5.0V) / 256 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 566 Digital Analog Converter (DAC_8B5V) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 567: Chapter 18 Scalable Controller Area Network (S12Mscanv3)
EMI environment of a vehicle, cost-effectiveness, and required bandwidth. MSCAN uses an advanced buffer arrangement resulting in predictable real-time behavior and simplified application software. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 568: Glossary
RXCAN Receive/ Transmit Engine TXCAN Transmit Interrupt Req. Message Receive Interrupt Req. Control Filtering Errors Interrupt Req. Status Buffering Wake-Up Interrupt Req. Configuration Registers Wake-Up Low Pass Filter Figure 18-1. MSCAN Block Diagram MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 569: Features
TXCAN and RXCAN is optional. 18.2.1 RXCAN — CAN Receiver Input Pin RXCAN is the MSCAN receiver input pin. 1. Depending on the actual bit timing and the clock jitter of the PLL. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 570: Txcan — Can Transmitter Output Pin
The MSCAN occupies 64 bytes in the memory space. The base address of the MSCAN module is determined at the MCU level when the MCU is defined. The register decode map is fixed and begins at the first address of the module address offset. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 571 0x0008 ABTRQ2 ABTRQ1 ABTRQ0 CANTARQ 0x0009 ABTAK2 ABTAK1 ABTAK0 CANTAAK 0x000A CANTBSEL 0x000B IDHIT2 IDHIT1 IDHIT0 IDAM1 IDAM0 CANIDAC 0x000C Reserved 0x000D BOHOLD CANMISC = Unimplemented or Reserved Figure 18-3. MSCAN Register Summary MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 572: Register Descriptions
All bits of all registers in this module are completely synchronous to internal clocks during a register read. 18.3.2.1 MSCAN Control Register 0 (CANCTL0) The CANCTL0 register provides various control bits of the MSCAN module as described below. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 573 Storage”). In loopback mode no receive timestamp is generated. The internal timer is reset (all bits set to 0) when disabled. This bit is held low in initialization mode. 0 Disable internal MSCAN timer 1 Enable internal MSCAN timer MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 574 RSTAT1 and RSTAT0 are not affected by initialization mode. 18.3.2.2 MSCAN Control Register 1 (CANCTL1) The CANCTL1 register provides various control bits and handshake status information of the MSCAN module as described below. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 575 0 MSCAN wakes up on any dominant level on the CAN bus 1 MSCAN wakes up only in case of a dominant pulse on the CAN bus that has a length of T MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 576 Baud Rate Prescaler — These bits determine the time quanta (Tq) clock which is used to build up the bit timing BRP[5:0] (see Table 18-7). Table 18-6. Synchronization Jump Width SJW1 SJW0 Synchronization Jump Width 1 Tq clock cycle 2 Tq clock cycles 3 Tq clock cycles 4 Tq clock cycles MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 577 Time Segment 1 — Time segments within the bit time fix the number of clock cycles per bit time and the location TSEG1[3:0] of the sample point (see Figure 18-44). Time segment 1 (TSEG1) values are programmable as shown in Table 18-10. In this case, PHASE_SEG1 must be at least 2 time quanta (Tq). MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 578 A flag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition which caused the setting is no longer valid. Every flag has an associated interrupt enable bit in the CANRIER register. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 579 00 RxOK: 96  receive error counter 128 01 RxWRN: 128  receive error counter 10 RxERR: : transmit error counter 11 Bus-off 1. The RSTAT[1:0], TSTAT[1:0] bits are not affected by initialization mode. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 580 The CANRIER register is held in the reset state when the initialization mode is active (INITRQ=1 and INITAK=1). This register is writable when not in initialization mode (INITRQ=0 and INITAK=0). The RSTATE[1:0], TSTATE[1:0] bits are not affected by initialization mode. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 581 RXSTAT[1:0] flags define an additional bus-off state for the receiver (see Section 18.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”). 18.3.2.7 MSCAN Transmitter Flag Register (CANTFLG) The transmit buffer empty flags each have an associated interrupt enable bit in the CANTIER register. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 582 0 The associated message buffer is full (loaded with a message due for transmission) 1 The associated message buffer is empty (not scheduled) 18.3.2.8 MSCAN Transmitter Interrupt Enable Register (CANTIER) This register contains the interrupt enable bits for the transmit buffer empty interrupt flags. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 583 The CANTARQ register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 584 1 The message was aborted. 18.3.2.11 MSCAN Transmit Buffer Selection Register (CANTBSEL) The CANTBSEL register allows the selection of the actual transmit message buffer, which then will be accessible in the CANTXFG register space. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 585 If all transmit message buffers are deselected, no accesses are allowed to the CANTXFG registers. 18.3.2.12 MSCAN Identifier Acceptance Control Register (CANIDAC) The CANIDAC register is used for identifier acceptance control as described below. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 586 The IDHITx indicators are always related to the message in the foreground buffer (RxFG). When a message gets shifted into the foreground buffer of the receiver FIFO the indicators are updated as well. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 587 Refer to Section 18.5.2, “Bus-Off Recovery,” for details. 0 Module is not bus-off or recovery has been requested by user in bus-off state 1 Module is bus-off and holds this state until user request MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 588 NOTE Reading this register when in any other mode other than sleep or initialization mode, may return an incorrect value. For MCUs with dual CPUs, this may result in a CPU fault condition. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 589 Module Base + 0x0018 to Module Base + 0x001B Access: User read/write Reset Figure 18-21. MSCAN Identifier Acceptance Registers (Second Bank) — CANIDAR4–CANIDAR7 Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 590 0 Match corresponding acceptance code register and identifier bits 1 Ignore corresponding acceptance code register bit Module Base + 0x001C to Module Base + 0x001F Access: User read/write Reset Figure 18-23. MSCAN Identifier Mask Registers (Second Bank) — CANIDMR4–CANIDMR7 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 591: Programmer's Model Of Message Storage
TIME bit is set (see Section 18.3.2.1, “MSCAN Control Register 0 (CANCTL0)”). The time stamp register is written by the MSCAN. The CPU can only read these registers. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 592 All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM-based implementation All reserved or unused bits of the receive and transmit buffers always read ‘x’. 1. Exception: The transmit buffer priority registers are 0 out of reset. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 593 ID16 ID15 IDR1 0x00X2 ID14 ID13 ID12 ID11 ID10 IDR2 0x00X3 IDR3 0x00X4 DSR0 0x00X5 DSR1 0x00X6 DSR2 0x00X7 DSR3 0x00X8 DSR4 0x00X9 DSR5 0x00XA DSR6 0x00XB DSR7 0x00XC DLC3 DLC2 DLC1 DLC0 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 594 The identifier registers for an extended format identifier consist of a total of 32 bits: ID[28:0], SRR, IDE, and RTR. The identifier registers for a standard format identifier consist of a total of 13 bits: ID[10:0], RTR, and IDE. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 595 Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the ID[17:15] most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 596 In the case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. In the case of a transmit buffer, this flag defines the setting of the RTR bit to be sent. 0 Data frame 1 Remote frame MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 597 CPU how to process the buffer identifier registers. In the case of a transmit buffer, the flag indicates to the MSCAN what type of identifier to send. 0 Standard format (11 bit) 1 Extended format (29 bit) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 598 DLR register. Module Base + 0x00X4 to Module Base + 0x00XB Reset: Figure 18-34. Data Segment Registers (DSR0–DSR7) — Extended Identifier Mapping Table 18-33. DSR0–DSR7 Register Field Descriptions Field Description Data bits 7-0 DB[7:0] MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 599 All transmission buffers with a cleared TXEx flag participate in the prioritization immediately before the SOF (start of frame) is sent. • The transmission buffer with the lowest local priority field wins the prioritization. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 600 Section 18.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 18.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). For receive buffers: Anytime when RXF is set. Write: Unimplemented MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 601: Functional Description
Section 18.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). For receive buffers: Anytime when RXF is set. Write: Unimplemented 18.4 Functional Description 18.4.1 General This section provides a complete functional description of the MSCAN. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 602: Message Storage
The MSCAN facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications. 18.4.2.1 Message Transmit Background Modern application layer software is built upon two fundamental assumptions: MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 603 The CPU then stores the identifier, the control bits, and the data content into one of the transmit buffers. Finally, the buffer is flagged as ready for transmission by clearing the associated TXE flag. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 604 1. The transmit interrupt occurs only if not masked. A polling scheme can be applied on TXEx also. 2. The receive interrupt occurs only if not masked. A polling scheme can be applied on RXF also. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 605: Identifier Acceptance Filter
32-bit filter bank (CANIDAR0–CANIDAR3, CANIDMR0–CANIDMR3) produces a filter 0 hit. Similarly, the second filter bank (CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7) produces a filter 1 hit. • Four identifier acceptance filters, each to be applied to: MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 606 IDR2 IDR3 CAN 2.0A/B ID10 ID10 ID10 IDR0 IDR1 IDR2 IDR3 Standard Identifier CANIDMR0 CANIDMR1 CANIDMR2 CANIDMR3 CANIDAR0 CANIDAR1 CANIDAR2 CANIDAR3 ID Accepted (Filter 0 Hit) Figure 18-40. 32-bit Maskable Identifier Acceptance Filter MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 607 ID10 ID10 IDR0 IDR1 IDR2 IDR3 Standard Identifier CANIDMR0 CANIDMR1 CANIDAR0 CANIDAR1 ID Accepted (Filter 0 Hit) CANIDMR2 CANIDMR3 CANIDAR2 CANIDAR3 ID Accepted (Filter 1 Hit) Figure 18-41. 16-bit Maskable Identifier Acceptance Filters MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 608 ID Accepted (Filter 0 Hit) CIDMR1 CIDAR1 ID Accepted (Filter 1 Hit) CIDMR2 CIDAR2 ID Accepted (Filter 2 Hit) CIDMR3 CIDAR3 ID Accepted (Filter 3 Hit) Figure 18-42. 8-bit Maskable Identifier Acceptance Filters MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 609 If the bus clock is generated from a PLL, it is recommended to select the oscillator clock rather than the bus clock due to jitter considerations, especially at the faster CAN bus rates. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 610 (PROP_SEG + PHASE_SEG1) (PHASE_SEG2) 4 ... 16 2 ... 8 8 ... 25 Time Quanta = 1 Bit Time Transmit Point Sample Point (single or triple sampling) Figure 18-44. Segments within the Bit Time MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 611: Modes Of Operation
0 .. 3 18.4.4 Modes of Operation 18.4.4.1 Normal System Operating Modes The MSCAN module behaves as described within this specification in all normal system operating modes. Write restrictions exist for some registers. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 612 CANTBSEL registers to their default values. In addition, the MSCAN enables the configuration of the CANBTR0, CANBTR1 bit timing registers; CANIDAC; and the CANIDAR, CANIDMR message filters. Section 18.3.2.1, “MSCAN Control Register 0 (CANCTL0),” for a detailed description of the initialization mode. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 613: Low-Power Options
Table 18-38 summarizes the combinations of MSCAN and CPU modes. A particular combination of modes is entered by the given settings on the CSWAI and SLPRQ/SLPAK bits. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 614 This is a non-power-saving mode. Enabling the MSCAN puts the module from disabled mode into normal mode. In this mode the module can either be in initialization mode or out of initialization mode. See Section 18.4.4.5, “MSCAN Initialization Mode”. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 615 RXF can be cleared. Shifting a new message into the foreground buffer of the receiver FIFO (RxFG) does not take place while in sleep mode. It is possible to access the transmit buffers and to clear the associated TXE flags. No message abort takes place while in sleep mode. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 616 In power down mode, all clocks are stopped and no registers can be accessed. If the MSCAN was not in sleep mode before power down mode became active, the module performs an internal recovery cycle after powering up. This causes some fixed delay before the module enters normal mode again. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 617: Reset Initialization
Transmit Interrupt At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. The TXEx flag of the empty message buffer is set. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 618 For this reason, bit manipulation instructions (BSET) must not be used to clear interrupt flags. These instructions may cause accidental clearing of interrupt flags which are set after entering the current interrupt service routine. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 619: Initialization/Application Information
128 occurrences of 11 consecutive recessive bits on the CAN bus have been monitored • BOHOLD in MSCAN Miscellaneous Register (CANMISC) has been cleared by the user These two events may occur in any order. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 620 Scalable Controller Area Network (S12MSCANV3) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 621: Chapter 19 Pulse-Width Modulator (S12Pwm8B8Cv2)
In freeze mode there is a software programmable option to disable the input clock to the prescaler. This is useful for emulation. Wait: The prescaler keeps on running, unless PSWAI in PWMCTL is set to 1. Freeze: The prescaler keeps on running, unless PFRZ in PWMCTL is set to 1. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 622: Block Diagram
The scalable PWM module has a selected number of external pins. Refer to device specification for exact number. 19.2.1 PWM7 - PWM0 — PWM Channel 7 - 0 Those pins serve as waveform output of PWM channel 7 - 0. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 623: Memory Map And Register Definition
0x0005 CON67 CON45 CON23 CON01 PSWAI PFRZ PWMCTL 0x0006 PWMCLKAB PCLKAB7 PCLKAB6 PCLKAB5 PCLKAB4 PCLKAB3 PCLKAB2 PCLKAB1 PCLKAB0 = Unimplemented or Reserved Figure 19-2. The scalable PWM Register Summary (Sheet 1 of 4) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 624 0x0013 Bit 7 Bit 0 PWMCNT7 0x0014 Bit 7 Bit 0 PWMPER0 0x0015 Bit 7 Bit 0 PWMPER1 = Unimplemented or Reserved Figure 19-2. The scalable PWM Register Summary (Sheet 1 of 4) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 625 Bit 7 Bit 0 PWMDTY5 0x0022 Bit 7 Bit 0 PWMDTY6 0x0023 Bit 7 Bit 0 PWMDTY7 0x0024 RESERVED = Unimplemented or Reserved Figure 19-2. The scalable PWM Register Summary (Sheet 1 of 4) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 626 While in run mode, if all existing PWM channels are disabled (PWMEx–0 = 0), the prescaler counter shuts off for power savings. Module Base + 0x0000 PWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0 Reset Figure 19-3. PWM Enable Register (PWME) Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 627 PWMPOL register. If the polarity bit is one, the PWM channel output is high at the beginning of the cycle and then goes low when the duty count is reached. Conversely, if the polarity bit is zero, the output starts low and then goes high when the duty count is reached. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 628 NOTE Register bits PCLK0 to PCLK7 can be written anytime. If a clock select is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 629 NOTE PCKB2–0 and PCKA2–0 register bits can be written anytime. If the clock pre-scale is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 630 Module Base + 0x0004 CAE7 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0 Reset Figure 19-7. PWM Center Align Enable Register (PWMCAE) Read: Anytime Write: Anytime NOTE Write these bits only when the corresponding channel is disabled. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 631 When channels 0 and 1 are concatenated, channel 0 registers become the high order bytes of the double byte channel. Section 19.4.2.7, “PWM 16-Bit Functions” for a more detailed description of the concatenation PWM Function. NOTE Change these bits only when both corresponding channels are disabled. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 632 1 Disable PWM input clock to the prescaler whenever the part is in freeze mode. This is useful for emulation. 19.3.2.7 PWM Clock A/B Select Register (PWMCLKAB) Each PWM channel has a choice of four clocks to use as the clock source for that channel as described below. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 633 0 Clock A or SA is the clock source for PWM channel 0, as shown in Table 19-5. 1 Clock B or SB is the clock source for PWM channel 0, as shown in Table 19-5. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 634 Any value written to this register will cause the scale counter to load the new scale value (PWMSCLB). Module Base + 0x0009 Bit 7 Bit 0 Reset Figure 19-11. PWM Scale B Register (PWMSCLB) Read: Anytime Write: Anytime (causes the scale counter to load the PWMSCLB value). MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 635 The period registers for each channel are double buffered so that if they change while the channel is enabled, the change will NOT take effect until one of the following occurs: • The effective period ends MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 636 The duty registers for each channel are double buffered so that if they change while the channel is enabled, the change will NOT take effect until one of the following occurs: • The effective period ends • The counter is written (counter resets to $00) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 637 This register is available only when the corresponding channel exists and is reserved if that channel does not exist. Writes to a reserved register have no functional effect. Reads from a reserved register return zeroes. Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 638: Functional Description
2. The rates available for clock SA are software selectable to be clock A divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. Similar rates are available for clock SB. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 639 PWM Ch 6 PCLK6 PCLKAB6 Clock to PWM Ch 7 PCLK7 PCLKAB7 Prescale Scale Clock Select Maximum possible channels, scalable in pairs from PWM0 to PWM7. Figure 19-15. PWM Clock Select Block Diagram MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 640 For channels 0, 1, 4, and 5 the clock choices are clock A. For channels 2, 3, 6, and 7 the clock choices are clock B. NOTE Changing clock control bits while channels are operating can cause irregularities in the PWM outputs. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 641: Pwm Channel Timers
PWMEx and the clock source. An exception to this is when channels are concatenated. Refer to Section 19.4.2.7, “PWM 16-Bit Functions” for more detail. NOTE The first PWM cycle after enabling the channel can be irregular. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 642 A match between the PWM counter and the period register behaves differently depending on what output mode is selected as shown in Figure 19-16 and described in Section 19.4.2.5, “Left Aligned Outputs” Section 19.4.2.6, “Center Aligned Outputs”. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 643 19-16, as well as performing a load from the double buffer period and duty register to the associated registers, as described in Section 19.4.2.3, “PWM Period and Duty”. The counter counts from 0 to the value in the period register – 1. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 644 PWMx Duty Cycle = 3/4 *100% = 75% The output waveform generated is shown in Figure 19-18. E = 100 ns Duty Cycle = 75% Period = 400 ns Figure 19-18. PWM Left Aligned Output Example Waveform MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 645 Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100% — Polarity = 1 (PPOLx = 1) Duty Cycle = [PWMDTYx / PWMPERx] * 100% As an example of a center aligned output, consider the following case: MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 646 0 and 1 are concatenated. The resulting PWM is output to the pins of the corresponding low order 8-bit channel as also shown in Figure 19-21. The polarity of the resulting PWM output is controlled by the PPOLx bit of the corresponding low order 8-bit channel as well. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 647 Once concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the low order PWMEx bit. In this case, the high order bytes PWMEx bits have no effect and their corresponding PWM output is disabled. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 648: Resets
• The 8-bit up/down counter is configured as an up counter out of reset. • All the channels are disabled and all the counters do not count. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 649: Interrupts
For channels 0, 1, 4, and 5 the clock choices are clock A. • For channels 2, 3, 6, and 7 the clock choices are clock B. 19.6 Interrupts The PWM module has no interrupt. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 650 Pulse-Width Modulator (S12PWM8B8CV2) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 651: Chapter 20 Serial Communication Interface (S12Sciv5)
IrDA: Infrared Design Associate IRQ: Interrupt Request LIN: Local Interconnect Network LSB: Least Significant Bit MSB: Most Significant Bit NRZ: Non-Return-to-Zero RZI: Return-to-Zero-Inverted RXD: Receive Pin SCI : Serial Communication Interface TXD: Transmit Pin MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 652: Features
Modes of Operation The SCI functions the same in normal, special, and emulation modes. It has two low power modes, wait and stop modes. • Run mode • Wait mode • Stop mode MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 653: Block Diagram
The RXD pin receives SCI (standard or infrared) data. An idle line is detected as a line high. This input is ignored when the receiver is disabled and should be terminated to a known voltage. 20.3 Memory Map and Register Definition This section provides a detailed description of all the SCI registers. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 654: Module Memory Map And Register Definition
BERRM1 BERRM0 BKDFE SCIACR2 0x0003 TCIE ILIE SCICR2 0x0004 TDRE RDRF IDLE SCISR1 0x0005 AMAP TXPOL RXPOL BRK13 TXDIR SCISR2 = Unimplemented or Reserved Figure 20-2. SCI Register Summary (Sheet 1 of 2) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 655 Those two registers are only visible in the memory map if AMAP = 0 (reset condition). The SCI baud rate register is used by to determine the baud rate of the SCI, and to control the infrared modulation/demodulation submodule. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 656 Figure 20-5. SCI Control Register 1 (SCICR1) Read: Anytime, if AMAP = 0. Write: Anytime, if AMAP = 0. NOTE This register is only visible in the memory map if AMAP = 0 (reset condition). MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 657 0 Even parity 1 Odd parity Table 20-5. Loop Functions LOOPS RSRC Function Normal operation Loop mode with transmitter output internally connected to receiver input Single-wire mode with TXD pin connected to receiver input MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 658 SCI Alternative Control Register 1 (SCIACR1) Module Base + 0x0001 RXEDGIE BERRIE BKDIE Reset = Unimplemented or Reserved Figure 20-7. SCI Alternative Control Register 1 (SCIACR1) Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 659 Receive input sampling occurs during the 9th time tick of a transmitted bit (refer to Figure 20-19) Receive input sampling occurs during the 13th time tick of a transmitted bit (refer to Figure 20-19) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 660 SCI. The TE bit can be used to queue an idle preamble. 0 Transmitter disabled 1 Transmitter enabled Receiver Enable Bit — RE enables the SCI receiver. 0 Receiver disabled 1 Receiver enabled MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 661 Module Base + 0x0004 TDRE RDRF IDLE Reset = Unimplemented or Reserved Figure 20-10. SCI Status Register 1 (SCISR1) Read: Anytime Write: Has no meaning or effect MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 662 RDRF flag but does not get set in the case of an overrun. Clear NF by reading SCI status register 1(SCISR1), and then reading SCI data register low (SCIDRL). 0 No noise 1 Noise MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 663 0 Normal polarity 1 Inverted polarity MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 664 Module Base + 0x0007 Reset Figure 20-13. SCI Data Registers (SCIDRL) Read: Anytime; reading accesses SCI receive data register Write: Anytime; writing accesses SCI transmit data register; writing to R8 has no effect MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 665: Functional Description
CPU and remote devices, including other CPUs. The SCI transmitter and receiver operate independently, although they use the same baud rate generator. The CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 666: Infrared Interface Submodule
The infrared submodule consists of two major blocks: the transmit encoder and the receive decoder. The SCI transmits serial bits of data which are encoded by the infrared submodule to transmit a narrow pulse MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 667: Lin Support
The SCI uses the standard NRZ mark/space data format. When Infrared is enabled, the SCI uses RZI data format where zeroes are represented by light pulses and ones remain low. See Figure 20-15 below. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 668 A frame with nine data bits has a total of 11 bits. Table 20-15. Example of 9-Bit Data Formats Start Data Address Parity Stop Bits Bits Bits The address bit identifies the frame as an address character. See Section 20.4.6.6, “Receiver Wakeup”. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 669: Baud Rate Generation
Error SBR[12:0] Clock (Hz) Clock (Hz) Baud Rate 609,756.1 38,109.8 38,400 308,642.0 19,290.1 19,200 153,374.2 9585.9 9,600 76,687.1 4792.9 4,800 38,402.5 2400.2 2,400 1302 19,201.2 1200.1 1,200 2604 9600.6 600.0 5208 4800.0 300.0 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 670: Transmitter
TXD pin, after it has prefaced them with a start bit and appended them with a stop bit. The SCI data registers (SCIDRH and SCIDRL) are the write-only buffers between the internal data bus and the transmit shift register. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 671 If the transmit interrupt enable bit, TIE, in SCI control register 2 (SCICR2) is also set, the TDRE flag generates a transmitter interrupt request. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 672 Does not clear the SCI data registers (SCIDRH/L) • May set noise flag NF, or receiver active flag RAF. 1. A Break character in this context are either 10 or 11 consecutive zero received bits MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 673 TDRE flag is set and immediately before writing the next byte to the SCI data register. If the TE bit is clear and the transmission is complete, the SCI is not the master of the TXD pin MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 674 If the bit error detect feature is disabled, the bit error interrupt flag is cleared. NOTE The RXPOL and TXPOL bit should be set the same when transmission collision detect feature is enabled, otherwise the bit error interrupt flag may be set incorrectly. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 675: Receiver
After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCISR1) becomes set, MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 676 Table 20-17. Start Bit Verification RT3, RT5, and RT7 Samples Start Bit Verification Noise Flag If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 677 The RT clock is reset and the start bit search begins again. The noise flag is not set because the noise occurred before the start bit was found. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 678 RT5 is high. The RT5 sample sets the noise flag. Although this is a worst-case misalignment of perceived bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 679 Depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may set the framing error flag. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 680 A noise error will occur if the RT8, RT9, and RT10 samples are not all the same logical values. A framing error will occur if the receiver clock is misaligned in such a way that the majority of the RT8, RT9, and RT10 stop bit samples are a logic zero. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 681 Fast Data Tolerance Figure 20-29 shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 682 Any receiver for which a message is not addressed can set its RWU bit and return to the standby state. The MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 683: Single-Wire Operation
(TE = 1 and RE = 1).The TXDIR bit (SCISR2[1]) determines whether the TXD pin is going to be used as an input (TXDIR = 0) or an output (TXDIR = 1) in this mode of operation. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 684: Loop Operation
If SCISWAI is set, SCI clock generation ceases and the SCI module enters a power-conservation state when the CPU is in wait mode. Setting SCISWAI does not affect the state of the receiver enable bit, RE, or the transmitter enable bit, TE. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 685: Interrupt Operation
The TDRE interrupt is set high by the SCI when the transmit shift register receives a byte from the SCI data register. A TDRE interrupt indicates that the transmit data register (SCIDRH/L) is empty and that a MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 686 LIN was detected. Clear BERRIF by writing a “1” to the SCIASR1 SCI alternative status register 1. This flag is also cleared if the bit error detect feature is disabled. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 687: Recovery From Wait Mode
The SCI interrupt request can be used to bring the CPU out of wait mode. 20.5.5 Recovery from Stop Mode An active edge on the receive input can be used to bring the CPU out of stop mode. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 688 Serial Communication Interface (S12SCIV5) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 689: Chapter 21 Serial Peripheral Interface (S12Spiv5)
The SPI includes these distinctive features: • Master mode and slave mode • Selectable 8 or 16-bit transfer width • Bidirectional mode • Slave select output • Mode fault error flag with CPU interrupt capability MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 690: Modes Of Operation
Figure 21-1 gives an overview on the SPI architecture. The main parts of the SPI are status, control and data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 691: External Signal Description
MOSI — Master Out/Slave In Pin This pin is used to transmit data out of the SPI module when it is configured as a master and receive data when it is configured as slave. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 692: Miso — Master In/Slave Out Pin
LSBFE SPICR1 0x0001 XFRW MODFEN BIDIROE SPISWAI SPC0 SPICR2 0x0002 SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 SPIBR 0x0003 SPIF SPTEF MODF SPISR 0x0004 SPIDRH = Unimplemented or Reserved Figure 21-2. SPI Register Summary MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 693: Register Descriptions
1 SPI enabled, port pins are dedicated to SPI functions. SPI Transmit Interrupt Enable — This bit enables SPI interrupt requests, if SPTEF flag is set. SPTIE 0 SPTEF interrupt disabled. 1 SPTEF interrupt enabled. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 694 SPI Control Register 2 (SPICR2) Module Base +0x0001 XFRW MODFEN BIDIROE SPISWAI SPC0 Reset = Unimplemented or Reserved Figure 21-4. SPI Control Register 2 (SPICR2) Read: Anytime Write: Anytime; writes to the reserved bits have no effect MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 695 Master In Master Out Bidirectional MISO not used by SPI Master In Master I/O Slave Mode of Operation Normal Slave Out Slave In Bidirectional Slave In MOSI not used by SPI Slave I/O MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 696 Table 21-6. Example SPI Baud Rate Selection (25 MHz Bus Clock) Baud Rate SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate Divisor 12.5 Mbit/s 6.25 Mbit/s 3.125 Mbit/s 1.5625 Mbit/s 781.25 kbit/s 390.63 kbit/s 195.31 kbit/s 97.66 kbit/s 6.25 Mbit/s 3.125 Mbit/s MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 697 1.25 Mbit/s 625 kbit/s 312.5 kbit/s 156.25 kbit/s 78.13 kbit/s 39.06 kbit/s 1280 19.53 kbit/s 2.08333 Mbit/s 1.04167 Mbit/s 520.83 kbit/s 260.42 kbit/s 130.21 kbit/s 65.10 kbit/s 32.55 kbit/s 1536 16.28 kbit/s 1.78571 Mbit/s MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 698 SPIF Interrupt Flag — This bit is set after received data has been transferred into the SPI data register. For SPIF information about clearing SPIF Flag, please refer to Table 21-8. 0 Transfer not yet complete. 1 New data copied to SPIDR. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 699 Byte Write to SPIDRH Byte Write to SPIDRL then Word Write to (SPIDRH:SPIDRL) Any write to SPIDRH or SPIDRL with SPTEF == 0 is effectively ignored. Data in SPIDRH is undefined in this case. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 700 If SPIF is set and valid data is in the receive shift register, and SPIF is serviced after the start of a third transmission, the data in the receive shift register has become invalid and is not transferred into the SPIDR (see Figure 21-10). MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 701: Functional Description
The SPI system is enabled by setting the SPI enable (SPE) bit in SPI control register 1. While SPE is set, the four associated SPI port pins are dedicated to the SPI function as: • Slave select (SS) • Serial clock (SCK) • Master out/slave in (MOSI) • Master in/slave out (MISO) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 702: Master Mode
SPI is in idle state. 1. n depends on the selected transfer width, please refer to Section 21.3.2.2, “SPI Control Register 2 (SPICR2) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 703: Slave Mode
Although the SPI is capable of duplex operation, some SPI peripherals are capable of only receiving SPI data in a slave mode. For these simpler devices, there is no serial data out pin. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 704: Transmission Formats
SHIFT REGISTER MOSI MOSI SHIFT REGISTER BAUD RATE GENERATOR Figure 21-11. Master/Slave Transfer Block Diagram 1. n depends on the selected transfer width, please refer to Section 21.3.2.2, “SPI Control Register 2 (SPICR2) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 705 MOSI signal is the output from the master. The SS pin of the master must be either high or reconfigured as a general-purpose output not affecting the SPI. 1. n depends on the selected transfer width, please refer to Section 21.3.2.2, “SPI Control Register 2 (SPICR2) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 706 = Minimum idling time between transfers (minimum SS high time) , and t are guaranteed for the master mode and required for the slave mode. Figure 21-12. SPI Clock Format 0 (CPHA = 0), with 8-bit Transfer Width selected (XFRW = 0) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 707 1. n depends on the selected transfer width, please refer to Section 21.3.2.2, “SPI Control Register 2 (SPICR2) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 708: Mc9S12G Family Reference Manual Rev.1.27 Nxp Semiconductors
The SS line is the slave select input to the slave. The SS pin of the master must be either high or reconfigured as a general-purpose output not affecting the SPI. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 709 = Minimum trailing time after the last SCK edge = Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers Figure 21-14. SPI Clock Format 1 (CPHA = 1), with 8-Bit Transfer Width selected (XFRW = 0) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 710: Spi Baud Rate Generation
The SPI clock rate is determined by the product of the value in the baud rate preselection bits (SPPR2–SPPR0) and the value in the baud rate selection bits (SPR2–SPR0). The module clock divisor equation is shown in Equation 21-3. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 711: Special Features
The MOSI pin becomes the serial data I/O (MOMI) pin for the master mode, and the MISO pin becomes serial data I/O (SISO) pin for the slave mode. The MISO pin in master mode and MOSI pin in slave mode are not used by the SPI. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 712: Error Conditions
In the special case where the SPI is in master mode and MODFEN bit is cleared, the SS pin is not used by the SPI. In this special case, the mode fault error function is inhibited and MODF remains cleared. In case MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 713: Low Power Mode Options
SPIDR to the master, it will continue to send the same byte. Else if the slave is currently sending the last received byte from the master, it will continue to send each previous master byte). MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 714 The MODF interrupt is reflected in the status register MODF flag. Clearing the flag will also clear the interrupt. This interrupt will stay active while the MODF flag is set. MODF has an automatic clearing process which is described in Section 21.3.2.4, “SPI Status Register (SPISR)”. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 715 SPTEF occurs when the SPI data register is ready to accept new data. After SPTEF is set, it does not clear until it is serviced. SPTEF has an automatic clearing process, which is described in Section 21.3.2.4, “SPI Status Register (SPISR)”. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 716 Serial Peripheral Interface (S12SPIV5) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 717: Chapter 22 Timer Module (Tim16B6Cv3)
The TIM16B6CV3 includes these distinctive features: • Up to 6 channels available. (refer to device specification for exact number) • All channels have same input capture/output compare functionality. • Clock prescaling. • 16-bit counter. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 718: Modes Of Operation
Timer channel 2 Input capture interrupt IOC4 Output compare Timer channel 3 interrupt Channel 5 Input capture Timer channel 4 IOC5 Output compare interrupt Timer channel 5 interrupt Figure 22-1. TIM16B6CV3 Block Diagram MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 719: External Signal Description
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 720 Bit 0 0x0024–0x002B Reserved 0x002C R RESERV RESERV OCPD5 OCPD4 OCPD3 OCPD2 OCPD1 OCPD0 OCPD 0x002D Reserved 0x002E PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 PTPSR 0x002F Reserved Figure 22-3. TIM16B6CV3 Register Summary MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 721 If forced output compare on any channel occurs at the same time as the successful output compare then forced output compare action will take precedence and interrupt flag won’t get set. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 722 22.3.2.4 Timer System Control Register 1 (TSCR1) Module Base + 0x0006 TSWAI TSFRZ TFFCA PRNT Reset = Unimplemented or Reserved Figure 22-8. Timer System Control Register 1 (TSCR1) Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 723 Timer Toggle On Overflow Register 1 (TTOV) Module Base + 0x0007 RESERVED RESERVED TOV5 TOV4 TOV3 TOV2 TOV1 TOV0 Reset Figure 22-9. Timer Toggle On Overflow Register 1 (TTOV) Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 724 OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output tied to OCx. Note: For an output line to be driven by an OCx the OCPDx must be cleared. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 725 Input Capture Edge Control — These six pairs of control bits configure the input capture edge detector circuits. EDGnB EDGnA Table 22-9. Edge Detector Circuit Configuration EDGnB EDGnA Configuration Capture disabled Capture on rising edges only Capture on falling edges only MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 726 22.3.2.9 Timer System Control Register 2 (TSCR2) Module Base + 0x000D RESERVED Reset = Unimplemented or Reserved Figure 22-15. Timer System Control Register 2 (TSCR2) Read: Anytime Write: Anytime. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 727 Figure 22-16. Main Timer Interrupt Flag 1 (TFLG1) Read: Anytime Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero will not affect current status of the bit. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 728 Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000. Clearing this bit requires writing a one to bit 7 of TFLG2 register while the TEN bit of TSCR1 is set to one. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 729 All timer input capture/output compare registers are reset to 0x0000. NOTE Read/Write access in byte mode for high byte should take place before low byte otherwise it will give a different result. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 730 22.3.2.14 Precision Timer Prescaler Select Register (PTPSR) Module Base + 0x002E PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 Reset Figure 22-21. Precision Timer Prescaler Select Register (PTPSR) Read: Anytime Write: Anytime All bits reset to zero. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 731: Functional Description
PTPS3 PTPS2 PTPS1 PTPS0 Factor 22.4 Functional Description This section provides a complete functional description of the timer TIM16B6CV3 block. Please refer to the detailed timer block diagram in Figure 22-22 as necessary. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 732: Prescaler
2 (TSCR2) are set to define a prescalar value that generates a divide by 1, 2, 4, 8, 16, 32, 64 and 128 when the PRNT bit in TSCR1 is disabled. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 733: Input Capture
OCPDx and TEN bits set to one. Set OCx: Write a 1 to FOCx while TEN=1, IOSx=1, OMx=1, OLx=1 and OCPDx=1 Clear OCx: Write a 1 to FOCx while TEN=1, IOSx=1, OMx=1, OLx=0 and OCPDx=1 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 734: Resets
22.6.2 Timer Overflow Interrupt (TOF) This active high output will be asserted by the module to request a timer overflow interrupt. The TIM block only generates the interrupt and does not service it. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 735: Chapter 23 Timer Module (Tim16B8Cv3)
23.1.1 Features The TIM16B8CV3 includes these distinctive features: • Up to 8 channels available. (refer to device specification for exact number) • All channels have same input capture/output compare functionality. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 736: Modes Of Operation
Timer counter keeps on running, unless TSFRZ in TSCR1 is set to 1. Wait: Counters keeps on running, unless TSWAI in TSCR1 is set to 1. Normal: Timer counter keep on running, unless TEN in TSCR1 is cleared to 0. 23.1.3 Block Diagrams MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 737 Input capture 16-bit IOC7 Pulse accumulator Output compare PA input interrupt Maximum possible channels, scalable from 0 to 7. Pulse Accumulator is available only if channel 7 exists. Figure 23-1. TIM16B8CV3 Block Diagram MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 738 IOC7 Interrupt PACNT Divide by 64 M clock Figure 23-2. 16-Bit Pulse Accumulator Block Diagram 16-bit Main Timer IOCn Edge detector Set CnF Interrupt TCn Input Capture Reg. Figure 23-3. Interrupt Flag Setting MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 739: External Signal Description
23-5. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the TIM16B8CV3 module and the address offset for each register. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 740: Register Descriptions
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0020 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PACTL Figure 23-5. TIM16B8CV3 Register Summary (Sheet 1 of 2) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 741 Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero. Field Description Input Capture or Output Compare Channel Configuration IOS[7:0] 0 The corresponding implemented channel acts as an input capture. 1 The corresponding implemented channel acts as an output compare. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 742 23.3.2.3 Output Compare 7 Mask Register (OC7M) Module Base + 0x0002 OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0 Reset Figure 23-8. Output Compare 7 Mask Register (OC7M) Read: Anytime Write: Anytime MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 743 7 mask register. 23.3.2.5 Timer Count Register (TCNT) Module Base + 0x0004 TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8 Reset Figure 23-10. Timer Count Register High (TCNTH) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 744 0 Allows the timer module to continue running during wait. 1 Disables the timer module when the MCU is in the wait mode. Timer interrupts cannot be used to get the MCU out of wait. TSWAI also affects pulse accumulator. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 745 When set, it takes precedence over forced output compare but not channel 7 override events. 0 Toggle output compare pin on overflow feature disabled. 1 Toggle output compare pin on overflow feature enabled. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 746 OCx the OCPDx must be cleared. Table 23-9. Compare Result Output Action Action No output compare action on the timer output signal Toggle OCx output line Clear OCx output line to zero Set OCx output line to one MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 747 EDG5A EDG4B EDG4A Reset Figure 23-16. Timer Control Register 3 (TCTL3) Module Base + 0x000B EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A Reset Figure 23-17. Timer Control Register 4 (TCTL4) Read: Anytime MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 748 Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in C7I:C0I the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set, the corresponding flag is enabled to cause a interrupt. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 749 Timer Clock Bus Clock / 1 Bus Clock / 2 Bus Clock / 4 Bus Clock / 8 Bus Clock / 16 Bus Clock / 32 Bus Clock / 64 Bus Clock / 128 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 750 TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit to one while TEN bit of TSCR1 or PAEN bit of PACTL is set to one. Read: Anytime Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared). MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 751 All timer input capture/output compare registers are reset to 0x0000. NOTE Read/Write access in byte mode for high byte should take place before low byte otherwise it will give a different result. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 752 23-20. CLK[1:0] Pulse Accumulator Overflow Interrupt Enable PAOVI 0 Interrupt inhibited. 1 Interrupt requested if PAOVF is set. Pulse Accumulator Input Interrupt Enable 0 Interrupt inhibited. 1 Interrupt requested if PAIF is set. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 753 When the TFFCA bit in the TSCR register is set, any access to the PACNT register will clear all the flags in the PAFLG register. Timer module or Pulse Accumulator must stay enabled (TEN=1 or PAEN=1) while clearing these bits. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 754 Reading the pulse accumulator counter registers immediately after an active edge on the pulse accumulator input pin may miss the last count because the input has to be synchronized with the Bus clock first. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 755 23.3.2.19 Precision Timer Prescaler Select Register (PTPSR) Module Base + 0x002E PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 Reset Figure 23-29. Precision Timer Prescaler Select Register (PTPSR) Read: Anytime Write: Anytime All bits reset to zero. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 756: Functional Description
PTPS3 PTPS2 PTPS1 PTPS0 Factor 23.4 Functional Description This section provides a complete functional description of the timer TIM16B8CV3 block. Please refer to the detailed timer block diagram in Figure 23-30 as necessary. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 757 PEDGE tim source DIVIDE-BY-64 PAOVI clock PAOVF PAIF PAOVF PAOVI Maximum possible channels, scalable from 0 to 7. Pulse Accumulator is available only if channel 7 exists. Figure 23-30. Detailed Timer Block Diagram MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 758: Prescaler
7 output compares to reset the timer counter. A channel 7 output compare can reset the timer counter even if the IOC7 pin is being used as the pulse accumulator input. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 759: Pulse Accumulator
Gated time accumulation mode — Counting pulses from a divide-by-64 clock. The PAMOD bit selects the mode of operation. The minimum pulse width for the PAI input is greater than two Bus clocks. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 760: Event Counter Mode
23.6 Interrupts This section describes interrupts originated by the TIM16B8CV3 block. Table 23-25 lists the interrupts generated by the TIM16B8CV3 to communicate with the MCU. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 761: Channel [7:0] Interrupt (C[7:0]F)
23.6.4 Timer Overflow Interrupt (TOF) This active high output will be asserted by the module to request a timer overflow interrupt. The TIM block only generates the interrupt and does not service it. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 762 Timer Module (TIM16B8CV3) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 763: Chapter 24 16 Kbyte Flash Module (S12Ftmrg16K1V1)
The Flash memory may be read as bytes and aligned words. Read access time is one bus cycle for bytes and aligned words. For misaligned words access, the CPU has to perform twice the byte read access command. For Flash memory, an erased bit reads 1 and a programmed bit reads 0. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 764: Glossary
512 bytes • Single bit fault correction and double bit fault detection within a 32-bit double word during read operations • Automated program and erase algorithm with verify and generation of ECC parity bits MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 765: Block Diagram
Interrupt generation on Flash command completion and Flash error detection • Security mechanism to prevent unauthorized access to the Flash memory 24.1.3 Block Diagram The block diagram of the Flash module is shown in Figure 24-1. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 766: External Signal Description
Security Clock Clock Divider FCLK Memory Controller EEPROM 256x22 sector 0 sector 1 sector 127 Figure 24-1. FTMRG16K1 Block Diagram 24.2 External Signal Description The Flash module contains no signals that connect off-chip. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 767: Memory Map And Registers
24-3.The P-Flash memory map is shown in Figure 24-2. Table 24-3. P-Flash Memory Addressing Size Global Address Description (Bytes) P-Flash Block 0x3_C000 – 0x3_FFFF 16 K Contains Flash Configuration Field (see Table 24-4) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 768 Movable End Flash Protected/Unprotected Higher Region 0x3_E000 2, 4, 8, 16 Kbytes Protection Fixed End 0x3_F000 0x3_F800 Flash Configuration Field P-Flash END = 0x3_FFFF 16 bytes (0x3_FF00 - 0x3_FF0F) Figure 24-2. P-Flash Memory Map MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 769 0x0_4200 – 0x0_57FF Reserved 0x0_5800 – 0x0_59FF Reserved 0x0_5A00 – 0x0_5FFF 1,536 Reserved 0x0_6000 – 0x0_6BFF 3,072 Reserved 0x0_6C00 – 0x0_7FFF 5,120 Reserved NVMRES - See Section 24.4.3 for NVMRES (NVM Resource) detail. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 770: Register Descriptions
Address & Name FDIVLD 0x0000 FDIVLCK FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 FCLKDIV KEYEN1 KEYEN0 RNV5 RNV4 RNV3 RNV2 SEC1 SEC0 0x0001 FSEC 0x0002 CCOBIX2 CCOBIX1 CCOBIX0 FCCOBIX Figure 24-4. FTMRG16K1 Register Summary MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 771 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 FCCOBHI 0x000B CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 FCCOBLO 0x000C FRSV1 0x000D FRSV2 0x000E FRSV3 0x000F FRSV4 0x0010 FOPT Figure 24-4. FTMRG16K1 Register Summary (continued) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 772 (CCIF=0). Table 24-7. FCLKDIV Field Descriptions Field Description Clock Divider Loaded FDIVLD 0 FCLKDIV register has not been written since the last reset 1 FCLKDIV register has been written since the last reset MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 773 BUSCLK is Greater Than this value. BUSCLK is Less Than or Equal to this value. 24.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 774 DISABLED ENABLED DISABLED Preferred KEYEN state to disable backdoor key access. Table 24-11. Flash Security States SEC[1:0] Status of Security SECURED SECURED UNSECURED SECURED Preferred SEC state to set MCU to secured state. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 775 All bits in the FRSV0 register read 0 and are not writable. 24.3.2.5 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array read access from the CPU. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 776 SFDIE interrupt enable in the FERCNFG register is set (see Section 24.3.2.6) 24.3.2.6 Flash Error Configuration Register (FERCNFG) The FERCNFG register enables the Flash error interrupts for the FERSTAT flags. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 777 Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see Section 24.6). CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable but not writable, while remaining bits read 0 and are not writable. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 778 Offset Module Base + 0x0007 DFDIF SFDIF Reset = Unimplemented or Reserved Figure 24-12. Flash Error Status Register (FERSTAT) All flags in the FERSTAT register are readable and only writable to clear the flag. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 779 If a double bit fault is detected while reading the P-Flash phrase containing the P-Flash protection byte during the reset sequence, the FPOPEN bit will be cleared and remaining bits in the FPROT register will be set to leave the P-Flash memory fully protected. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 780 The P-Flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 781 1 Disables EEPROM memory protection from program and erase 4–0 EEPROM Protection Size — The DPS[4:0] bits determine the size of the protected area in the EEPROM DPS[4:0] memory as shown inTable 24-21 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 782 NVM command mode uses the indexed FCCOB register to provide a command code and its relevant parameters to the Memory Controller. The user first sets up all required FCCOB fields and then initiates MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 783 This Flash register is reserved for factory testing. Offset Module Base + 0x000C Reset = Unimplemented or Reserved Figure 24-17. Flash Reserved1 Register (FRSV1) All bits in the FRSV1 register read 0 and are not writable. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 784 This Flash register is reserved for factory testing. Offset Module Base + 0x000F Reset = Unimplemented or Reserved Figure 24-20. Flash Reserved4 Register (FRSV4) All bits in the FRSV4 register read 0 and are not writable. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 785 = Unimplemented or Reserved Figure 24-22. Flash Reserved5 Register (FRSV5) All bits in the FRSV5 register read 0 and are not writable. 24.3.2.18 Flash Reserved6 Register (FRSV6) This Flash register is reserved for factory testing. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 786 This Flash register is reserved for factory testing. Offset Module Base + 0x0013 Reset = Unimplemented or Reserved Figure 24-24. Flash Reserved7 Register (FRSV7) All bits in the FRSV7 register read 0 and are not writable. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 787: Functional Description
Prior to issuing any Flash program or erase command after a reset, the user is required to write the FCLKDIV register to divide BUSCLK down to a target FCLK of 1 MHz. Table 24-8 shows recommended values for the FDIV field based on BUSCLK frequency. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 788 Flash command has completed. Upon completion, the Memory Controller will return CCIF to 1 and the FCCOB register will be used to communicate any results. The flow for a generic command write sequence is shown in Figure 24-25. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 789 More Parameters? Write: FSTAT register (to launch command) Clear CCIF 0x80 Read: FSTAT register Bit Polling for Command Completion CCIF Set? Check EXIT Figure 24-25. Generic Flash Command Write Sequence Flowchart MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 790 P-Flash block and other resources within the Flash module. Table 24-26. P-Flash Commands FCMD Command Function on P-Flash Memory Erase Verify All Verify that all P-Flash (and EEPROM) blocks are erased. 0x01 Blocks MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 791 Table 24-27. EEPROM Commands FCMD Command Function on EEPROM Memory Erase Verify All Verify that all EEPROM (and P-Flash) blocks are erased. 0x01 Blocks 0x02 Erase Verify Block Verify that the EEPROM block is erased. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 792: Allowed Simultaneous P-Flash And Eeprom Operations
‘Set User Margin Level’ or ‘Set Field Margin Level’ with anything but the ‘normal’ level specified. See the Note on margin settings in Section 24.4.6.12 Section 24.4.6.13. The ‘Mass Erase’ operations are commands ‘Erase All Blocks’ and ‘Erase Flash Block’ MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 793: Flash Command Description
Set if any errors have been encountered during the read or if blank check failed . Set if any non-correctable errors have been encountered during the read or if MGSTAT0 blank check failed. As found in the memory map for FTMRG32K1. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 794 The Erase Verify P-Flash Section command will verify that a section of code in the P-Flash memory is erased. The Erase Verify P-Flash Section command defines the starting point of the code to be verified and the number of phrases. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 795 Table 24-36. Read Once Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 0x04 Not Required Read Once phrase index (0x0000 - 0x0007) Read Once word 0 value Read Once word 1 value Read Once word 2 value MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 796 Upon clearing CCIF to launch the Program P-Flash command, the Memory Controller will program the data words to the supplied global address and will then proceed to verify the data words read back as expected. The CCIF flag will set after the Program P-Flash operation has completed. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 797 Valid phrase index values for the Program Once command range from 0x0000 to 0x0007. During execution of the Program Once command, any attempt to read addresses within P-Flash will return invalid data. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 798 Set if any non-correctable errors have been encountered during the verify MGSTAT0 operation As found in the memory map for FTMRG32K1. 24.4.6.8 Erase Flash Block Command The Erase Flash Block operation will erase all addresses in a P-Flash or EEPROM block. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 799 Upon clearing CCIF to launch the Erase P-Flash Sector command, the Memory Controller will erase the selected Flash sector and then verify that it is erased. The CCIF flag will be set after the Erase P-Flash Sector operation has completed. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 800 MGSTAT1 Set if any errors have been encountered during the verify operation Set if any non-correctable errors have been encountered during the verify MGSTAT0 operation As found in the memory map for FTMRG32K1. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 801 MGSTAT0 None 24.4.6.12 Set User Margin Level Command The Set User Margin Level command causes the Memory Controller to set the margin level for future read operations of the P-Flash or EEPROM block. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 802 Set if command not available in current mode (see Table 24-25) ACCERR Set if an invalid FlashBlockSelectionCode[1:0] is supplied (See Table 24-32 FSTAT Set if an invalid margin level setting is supplied FPVIOL None MGSTAT1 None MGSTAT0 None MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 803 0x0000 Return to Normal Level 0x0001 User Margin-1 Level 0x0002 User Margin-0 Level 0x0003 Field Margin-1 Level 0x0004 Field Margin-0 Level Read margin to the erased state Read margin to the programmed state MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 804 EEPROM memory is erased. The CCIF flag will set after the Erase Verify EEPROM Section operation has completed. If the section is not erased, it means blank check failed, both MGSTAT bits will be set. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 805 Memory Controller and be programmed if the area is unprotected. The CCOBIX index value at Program EEPROM command launch determines how many words will be programmed in the EEPROM block. The CCIF flag is set when the operation has completed. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 806 Set if the selected area of the EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation Set if any non-correctable errors have been encountered during the verify MGSTAT0 operation MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 807: Interrupts
The logic used for generating the Flash module interrupts is shown in Figure 24-26. Flash Command Interrupt Request CCIE CCIF DFDIE DFDIF Flash Error Interrupt Request SFDIE SFDIF Figure 24-26. Flash Module Interrupts Implementation MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 808: Wait Mode
24-11) will be changed to unsecure the MCU. Key values of 0x0000 and 0xFFFF are not permitted as backdoor keys. While the Verify Backdoor Access Key command is active, P-Flash memory and EEPROM memory will not be available for read access and will return invalid data. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 809: Unsecuring The Mcu In Special Single Chip Mode Using Bdm
Flash security byte may be programmed to the unsecure state by continuing with the following steps: 7. Send BDM commands to execute the Program P-Flash command write sequence to program the Flash security byte to the unsecured state MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 810: Mode And Security Effects On Flash Command Availability
CCIF high which enables user commands. If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 811: Chapter 25 32 Kbyte Flash Module (S12Ftmrg32K1V1)
The Flash memory may be read as bytes and aligned words. Read access time is one bus cycle for bytes and aligned words. For misaligned words access, the CPU has to perform twice the byte read access command. For Flash memory, an erased bit reads 1 and a programmed bit reads 0. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 812: Glossary
512 bytes • Single bit fault correction and double bit fault detection within a 32-bit double word during read operations • Automated program and erase algorithm with verify and generation of ECC parity bits MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 813: Block Diagram
Interrupt generation on Flash command completion and Flash error detection • Security mechanism to prevent unauthorized access to the Flash memory 25.1.3 Block Diagram The block diagram of the Flash module is shown in Figure 25-1. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 814: External Signal Description
Security Clock Clock Divider FCLK Memory Controller EEPROM 512x22 sector 0 sector 1 sector 255 Figure 25-1. FTMRG32K1 Block Diagram 25.2 External Signal Description The Flash module contains no signals that connect off-chip. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 815: Memory Map And Registers
25-3.The P-Flash memory map is shown in Figure 25-2. Table 25-3. P-Flash Memory Addressing Size Global Address Description (Bytes) P-Flash Block 0x3_8000 – 0x3_FFFF 32 K Contains Flash Configuration Field (see Table 25-4) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 816 Section 25.3.2.2, “Flash Security Register (FSEC)” 0x3FF08-0x3_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0x3_FF08 - 0x3_FF0B reserved field should be programmed to 0xFF. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 817 0x0_4008 – 0x0_40B5 Reserved 0x0_40B6 – 0x0_40B7 Version ID 0x0_40B8 – 0x0_40BF Reserved Program Once Field 0x0_40C0 – 0x0_40FF Refer to Section 25.4.6.6, “Program Once Command” Used to track firmware patch versions, see Section 25.4.2 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 818: Register Descriptions
The Flash module contains a set of 20 control and status registers located between Flash module base + 0x0000 and 0x0013. In the case of the writable registers, the write accesses are forbidden during Fash command execution (for more detail, see Caution note in Section 25.3). MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 819 DPS4 DPS3 DPS2 DPS1 DPS0 EEPROT 0x000A CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 FCCOBHI 0x000B CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 FCCOBLO 0x000C FRSV1 Figure 25-4. FTMRG32K1 Register Summary MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 820 All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times but bit 7 remains unwritable. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 821 10.6 11.6 0x0A 11.6 12.6 0x0B 12.6 13.6 0x0C 13.6 14.6 0x0D 14.6 15.6 0x0E 15.6 16.6 0x0F BUSCLK is Greater Than this value. BUSCLK is Less Than or Equal to this value. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 822 Flash module is unsecured using backdoor key access, the SEC bits are forced to 10. Table 25-10. Flash KEYEN States KEYEN[1:0] Status of Backdoor Key Access DISABLED DISABLED ENABLED DISABLED Preferred KEYEN state to disable backdoor key access. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 823 This Flash register is reserved for factory testing. Offset Module Base + 0x000C Reset = Unimplemented or Reserved Figure 25-8. Flash Reserved0 Register (FRSV0) All bits in the FRSV0 register read 0 and are not writable. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 824 SFDIE interrupt enable in the FERCNFG register is set (see Section 25.3.2.6) 25.3.2.6 Flash Error Configuration Register (FERCNFG) The FERCNFG register enables the Flash error interrupts for the FERSTAT flags. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 825 Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see Section 25.6). CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable but not writable, while remaining bits read 0 and are not writable. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 826 Offset Module Base + 0x0007 DFDIF SFDIF Reset = Unimplemented or Reserved Figure 25-12. Flash Error Status Register (FERSTAT) All flags in the FERSTAT register are readable and only writable to clear the flag. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 827 If a double bit fault is detected while reading the P-Flash phrase containing the P-Flash protection byte during the reset sequence, the FPOPEN bit will be cleared and remaining bits in the FPROT register will be set to leave the P-Flash memory fully protected. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 828 Protected Low Range Protected High Range Protected High and Low Ranges Full P-Flash Memory Protected Unprotected Low Range Unprotected High Range Unprotected High and Low Ranges For range sizes, refer to Table 25-19 Table 25-20. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 829 Flash memory at global address 0x3_FF0C during the reset sequence, it can be changed by the user. The P-Flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 830 Scenario FLASH START 0x3_8000 0x3_FFFF Protected region with size Unprotected region defined by FPLS Protected region Protected region with size not defined by FPLS, FPHS defined by FPHS Figure 25-14. P-Flash Protection Scenarios MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 831 Writes must increase the DPS value and the DPOPEN bit can only be written from 1 (protection disabled) to 0 (protection enabled). If the DPOPEN bit is set, the state of the DPS bits is irrelevant. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 832 0x0_0400 – 0x0_04BF 192 bytes The Protection Size goes on enlarging in step of 32 bytes, for each DPS value increasing of one. 11111 - to - 11111 0x0_0400 – 0x0_07FF 1,024 bytes MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 833 Section 25.4.6. Table 25-24. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] Byte FCCOB Parameter Fields (NVM Command Mode) FCMD[7:0] defining Flash command 6’h0, Global address [17:16] Global address [15:8] Global address [7:0] MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 834 = Unimplemented or Reserved Figure 25-19. Flash Reserved2 Register (FRSV2) All bits in the FRSV2 register read 0 and are not writable. 25.3.2.14 Flash Reserved3 Register (FRSV3) This Flash register is reserved for factory testing. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 835 F in Figure 25-22. If a double bit fault is detected while reading the P-Flash phrase containing the Flash nonvolatile byte during the reset sequence, all bits in the FOPT register will be set. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 836 = Unimplemented or Reserved Figure 25-24. Flash Reserved6 Register (FRSV6) All bits in the FRSV6 register read 0 and are not writable. 25.3.2.19 Flash Reserved7 Register (FRSV7) This Flash register is reserved for factory testing. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 837: Functional Description
IFR Version ID Word The version ID word is stored in the IFR at address 0x0_40B6. The contents of the word are defined in Table 25-26. Table 25-26. IFR Version ID Fields [15:4] [3:0] Reserved VERNUM MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 838: Internal Nvm Resource (Nvmres)
25.3.2.7) and the CCIF flag should be tested to determine the status of the current command write sequence. If CCIF is 0, the previous command write sequence is still active, a new command write sequence cannot be started, and all writes to the FCCOB register are ignored. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 839: Mc9S12G Family Reference Manual Rev.1.27 Nxp Semiconductors
Flash command has completed. Upon completion, the Memory Controller will return CCIF to 1 and the FCCOB register will be used to communicate any results. The flow for a generic command write sequence is shown in Figure 25-26. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 840 More Parameters? Write: FSTAT register (to launch command) Clear CCIF 0x80 Read: FSTAT register Bit Polling for Command Completion CCIF Set? Check EXIT Figure 25-26. Generic Flash Command Write Sequence Flowchart MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 841 P-Flash block and other resources within the Flash module. Table 25-28. P-Flash Commands FCMD Command Function on P-Flash Memory Erase Verify All Verify that all P-Flash (and EEPROM) blocks are erased. 0x01 Blocks MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 842 Table 25-29. EEPROM Commands FCMD Command Function on EEPROM Memory Erase Verify All Verify that all EEPROM (and P-Flash) blocks are erased. 0x01 Blocks 0x02 Erase Verify Block Verify that the EEPROM block is erased. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 843: Allowed Simultaneous P-Flash And Eeprom Operations
‘Set User Margin Level’ or ‘Set Field Margin Level’ with anything but the ‘normal’ level specified. See the Note on margin settings in Section 25.4.6.12 Section 25.4.6.13. The ‘Mass Erase’ operations are commands ‘Erase All Blocks’ and ‘Erase Flash Block’ MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 844: Flash Command Description
Set if any errors have been encountered during the read or if blank check failed . Set if any non-correctable errors have been encountered during the read or if MGSTAT0 blank check failed. As found in the memory map for FTMRG32K1. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 845 The Erase Verify P-Flash Section command will verify that a section of code in the P-Flash memory is erased. The Erase Verify P-Flash Section command defines the starting point of the code to be verified and the number of phrases. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 846 CCOBIX[2:0] FCCOB Parameters 0x04 Not Required Read Once phrase index (0x0000 - 0x0007) Read Once word 0 value Read Once word 1 value Read Once word 2 value Read Once word 3 value MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 847 Upon clearing CCIF to launch the Program P-Flash command, the Memory Controller will program the data words to the supplied global address and will then proceed to verify the data words read back as expected. The CCIF flag will set after the Program P-Flash operation has completed. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 848 Valid phrase index values for the Program Once command range from 0x0000 to 0x0007. During execution of the Program Once command, any attempt to read addresses within P-Flash will return invalid data. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 849 Set if any non-correctable errors have been encountered during the verify MGSTAT0 operation As found in the memory map for FTMRG32K1. 25.4.6.8 Erase Flash Block Command The Erase Flash Block operation will erase all addresses in a P-Flash or EEPROM block. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 850 Upon clearing CCIF to launch the Erase P-Flash Sector command, the Memory Controller will erase the selected Flash sector and then verify that it is erased. The CCIF flag will be set after the Erase P-Flash Sector operation has completed. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 851 The Verify Backdoor Access Key command will only execute if it is enabled by the KEYEN bits in the FSEC register (see Table 25-10). The Verify Backdoor Access Key command releases security if MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 852 The Set User Margin Level command causes the Memory Controller to set the margin level for future read operations of the P-Flash or EEPROM block. Table 25-54. Set User Margin Level Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters Flash block selection code [1:0] . See 0x0D Table 25-34 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 853 Set if command not available in current mode (see Table 25-27) ACCERR Set if an invalid FlashBlockSelectionCode[1:0] is supplied (See Table 25-34 FSTAT Set if an invalid margin level setting is supplied FPVIOL None MGSTAT1 None MGSTAT0 None MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 854 0x0000 Return to Normal Level 0x0001 User Margin-1 Level 0x0002 User Margin-0 Level 0x0003 Field Margin-1 Level 0x0004 Field Margin-0 Level Read margin to the erased state Read margin to the programmed state MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 855 EEPROM memory is erased. The CCIF flag will set after the Erase Verify EEPROM Section operation has completed. If the section is not erased, it means blank check failed, both MGSTAT bits will be set. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 856 Memory Controller and be programmed if the area is unprotected. The CCOBIX index value at Program EEPROM command launch determines how many words will be programmed in the EEPROM block. The CCIF flag is set when the operation has completed. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 857 Set if the selected area of the EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation Set if any non-correctable errors have been encountered during the verify MGSTAT0 operation MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 858: Interrupts
The logic used for generating the Flash module interrupts is shown in Figure 25-27. Flash Command Interrupt Request CCIE CCIF DFDIE DFDIF Flash Error Interrupt Request SFDIE SFDIF Figure 25-27. Flash Module Interrupts Implementation MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 859: Wait Mode
25-11) will be changed to unsecure the MCU. Key values of 0x0000 and 0xFFFF are not permitted as backdoor keys. While the Verify Backdoor Access Key command is active, P-Flash memory and EEPROM memory will not be available for read access and will return invalid data. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 860: Unsecuring The Mcu In Special Single Chip Mode Using Bdm
Flash security byte may be programmed to the unsecure state by continuing with the following steps: 7. Send BDM commands to execute the Program P-Flash command write sequence to program the Flash security byte to the unsecured state MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 861: Mode And Security Effects On Flash Command Availability
CCIF high which enables user commands. If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 862 32 KByte Flash Module (S12FTMRG32K1V1) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 863: Chapter 26 48 Kbyte Flash Module (S12Ftmrg48K1V1)
The Flash memory may be read as bytes and aligned words. Read access time is one bus cycle for bytes and aligned words. For misaligned words access, the CPU has to perform twice the byte read access command. For Flash memory, an erased bit reads 1 and a programmed bit reads 0. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 864: Glossary
512 bytes • Single bit fault correction and double bit fault detection within a 32-bit double word during read operations • Automated program and erase algorithm with verify and generation of ECC parity bits MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 865 No external high-voltage power supply required for Flash memory program and erase operations • Interrupt generation on Flash command completion and Flash error detection • Security mechanism to prevent unauthorized access to the Flash memory MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 866: Block Diagram
1 Interrupt Request sector 95 Security Clock Clock Divider FCLK Memory Controller EEPROM 768x22 sector 0 sector 1 sector 383 26.2 External Signal Description The Flash module contains no signals that connect off-chip. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 867: Memory Map And Registers
Section 26.4.3 26.3.1 Module Memory Map The S12 architecture places the P-Flash memory between global addresses 0x3_4000 and 0x3_FFFF as shown in Table 26-3 .The P-Flash memory map is shown in Figure 26-2. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 868 Default protection settings as well as security information that allows the MCU to restrict access to the Flash module are stored in the Flash configuration field as described in Table 26-4. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 869 Section 26.3.2.2, “Flash Security Register (FSEC)” 0x3FF08-0x3_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0x3_FF08 - 0x3_FF0B reserved field should be programmed to 0xFF. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 870 0x0_4008 – 0x0_40B5 Reserved 0x0_40B6 – 0x0_40B7 Version ID 0x0_40B8 – 0x0_40BF Reserved Program Once Field 0x0_40C0 – 0x0_40FF Refer to Section 26.4.6.6, “Program Once Command” Used to track firmware patch versions, see Section 26.4.2 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 871: Register Descriptions
The Flash module contains a set of 20 control and status registers located between Flash module base + 0x0000 and 0x0013. In the case of the writable registers, the write accesses are forbidden during Fash command execution (for more detail, see Caution note in Section 26.3). MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 872 DPS4 DPS3 DPS2 DPS1 DPS0 EEPROT 0x000A CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 FCCOBHI 0x000B CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 FCCOBLO 0x000C FRSV1 Figure 26-4. FTMRG48K1 Register Summary MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 873 All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times but bit 7 remains unwritable. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 874 10.6 11.6 0x0A 11.6 12.6 0x0B 12.6 13.6 0x0C 13.6 14.6 0x0D 14.6 15.6 0x0E 15.6 16.6 0x0F BUSCLK is Greater Than this value. BUSCLK is Less Than or Equal to this value. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 875 Flash module is unsecured using backdoor key access, the SEC bits are forced to 10. Table 26-10. Flash KEYEN States KEYEN[1:0] Status of Backdoor Key Access DISABLED DISABLED ENABLED DISABLED Preferred KEYEN state to disable backdoor key access. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 876 This Flash register is reserved for factory testing. Offset Module Base + 0x000C Reset = Unimplemented or Reserved Figure 26-8. Flash Reserved0 Register (FRSV0) All bits in the FRSV0 register read 0 and are not writable. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 877 SFDIE interrupt enable in the FERCNFG register is set (see Section 26.3.2.6) 26.3.2.6 Flash Error Configuration Register (FERCNFG) The FERCNFG register enables the Flash error interrupts for the FERSTAT flags. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 878 Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see Section 26.6). CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable but not writable, while remaining bits read 0 and are not writable. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 879 Offset Module Base + 0x0007 DFDIF SFDIF Reset = Unimplemented or Reserved Figure 26-12. Flash Error Status Register (FERSTAT) All flags in the FERSTAT register are readable and only writable to clear the flag. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 880 If a double bit fault is detected while reading the P-Flash phrase containing the P-Flash protection byte during the reset sequence, the FPOPEN bit will be cleared and remaining bits in the FPROT register will be set to leave the P-Flash memory fully protected. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 881 Protected Low Range Protected High Range Protected High and Low Ranges Full P-Flash Memory Protected Unprotected Low Range Unprotected High Range Unprotected High and Low Ranges For range sizes, refer to Table 26-19 Table 26-20. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 882 Flash memory at global address 0x3_FF0C during the reset sequence, it can be changed by the user. The P-Flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 883 Scenario FLASH START 0x3_8000 0x3_FFFF Protected region with size Unprotected region defined by FPLS Protected region Protected region with size not defined by FPLS, FPHS defined by FPHS Figure 26-14. P-Flash Protection Scenarios MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 884 Writes must increase the DPS value and the DPOPEN bit can only be written from 1 (protection disabled) to 0 (protection enabled). If the DPOPEN bit is set, the state of the DPS bits is irrelevant. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 885 0x0_0400 – 0x0_04BF 192 bytes The Protection Size goes on enlarging in step of 32 bytes, for each DPS value increasing of one. 101111 - to - 111111 0x0_0400 – 0x0_09FF 1,536 bytes MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 886 Section 26.4.6. Table 26-24. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] Byte FCCOB Parameter Fields (NVM Command Mode) FCMD[7:0] defining Flash command 6’h0, Global address [17:16] Global address [15:8] Global address [7:0] MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 887 = Unimplemented or Reserved Figure 26-19. Flash Reserved2 Register (FRSV2) All bits in the FRSV2 register read 0 and are not writable. 26.3.2.14 Flash Reserved3 Register (FRSV3) This Flash register is reserved for factory testing. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 888 F in Figure 26-22. If a double bit fault is detected while reading the P-Flash phrase containing the Flash nonvolatile byte during the reset sequence, all bits in the FOPT register will be set. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 889 = Unimplemented or Reserved Figure 26-24. Flash Reserved6 Register (FRSV6) All bits in the FRSV6 register read 0 and are not writable. 26.3.2.19 Flash Reserved7 Register (FRSV7) This Flash register is reserved for factory testing. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 890: Functional Description
IFR Version ID Word The version ID word is stored in the IFR at address 0x0_40B6. The contents of the word are defined in Table 26-26. Table 26-26. IFR Version ID Fields [15:4] [3:0] Reserved VERNUM MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 891: Internal Nvm Resource (Nvmres)
26.3.2.7) and the CCIF flag should be tested to determine the status of the current command write sequence. If CCIF is 0, the previous command write sequence is still active, a new command write sequence cannot be started, and all writes to the FCCOB register are ignored. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 892 Flash command has completed. Upon completion, the Memory Controller will return CCIF to 1 and the FCCOB register will be used to communicate any results. The flow for a generic command write sequence is shown in Figure 26-26. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 893 More Parameters? Write: FSTAT register (to launch command) Clear CCIF 0x80 Read: FSTAT register Bit Polling for Command Completion CCIF Set? Check EXIT Figure 26-26. Generic Flash Command Write Sequence Flowchart MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 894 P-Flash block and other resources within the Flash module. Table 26-28. P-Flash Commands FCMD Command Function on P-Flash Memory Erase Verify All Verify that all P-Flash (and EEPROM) blocks are erased. 0x01 Blocks MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 895 Table 26-29. EEPROM Commands FCMD Command Function on EEPROM Memory Erase Verify All Verify that all EEPROM (and P-Flash) blocks are erased. 0x01 Blocks 0x02 Erase Verify Block Verify that the EEPROM block is erased. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 896: Allowed Simultaneous P-Flash And Eeprom Operations
‘Set User Margin Level’ or ‘Set Field Margin Level’ with anything but the ‘normal’ level specified. See the Note on margin settings in Section 26.4.6.12 Section 26.4.6.13. The ‘Mass Erase’ operations are commands ‘Erase All Blocks’ and ‘Erase Flash Block’ MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 897: Flash Command Description
MGSTAT1 Set if any errors have been encountered during the reador if blank check failed . Set if any non-correctable errors have been encountered during the read or if MGSTAT0 blank check failed. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 898 The Erase Verify P-Flash Section command will verify that a section of code in the P-Flash memory is erased. The Erase Verify P-Flash Section command defines the starting point of the code to be verified and the number of phrases. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 899 CCOBIX[2:0] FCCOB Parameters 0x04 Not Required Read Once phrase index (0x0000 - 0x0007) Read Once word 0 value Read Once word 1 value Read Once word 2 value Read Once word 3 value MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 900 Upon clearing CCIF to launch the Program P-Flash command, the Memory Controller will program the data words to the supplied global address and will then proceed to verify the data words read back as expected. The CCIF flag will set after the Program P-Flash operation has completed. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 901 Valid phrase index values for the Program Once command range from 0x0000 to 0x0007. During execution of the Program Once command, any attempt to read addresses within P-Flash will return invalid data. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 902 Set if any non-correctable errors have been encountered during the verify MGSTAT0 operation 26.4.6.8 Erase Flash Block Command The Erase Flash Block operation will erase all addresses in a P-Flash or EEPROM block. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 903 Upon clearing CCIF to launch the Erase P-Flash Sector command, the Memory Controller will erase the selected Flash sector and then verify that it is erased. The CCIF flag will be set after the Erase P-Flash Sector operation has completed. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 904 The Verify Backdoor Access Key command will only execute if it is enabled by the KEYEN bits in the FSEC register (see Table 26-10). The Verify Backdoor Access Key command releases security if user-supplied keys match those stored in the Flash security bytes of the Flash configuration field (see MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 905 The Set User Margin Level command causes the Memory Controller to set the margin level for future read operations of the P-Flash or EEPROM block. Table 26-54. Set User Margin Level Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 0x0D Flash block selection code [1:0] . See Margin level setting. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 906 User margin levels can be used to check that Flash memory contents have adequate margin for normal level read operations. If unexpected results are encountered when checking Flash memory contents at user margin levels, a potential loss of information has been detected. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 907 0x0000 Return to Normal Level 0x0001 User Margin-1 Level 0x0002 User Margin-0 Level 0x0003 Field Margin-1 Level 0x0004 Field Margin-0 Level Read margin to the erased state Read margin to the programmed state MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 908 EEPROM memory is erased. The CCIF flag will set after the Erase Verify EEPROM Section operation has completed. If the section is not erased, it means blank check failed, both MGSTAT bits will be set. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 909 Memory Controller and be programmed if the area is unprotected. The CCOBIX index value at Program EEPROM command launch determines how many words will be programmed in the EEPROM block. The CCIF flag is set when the operation has completed. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 910 Set if the selected area of the EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation Set if any non-correctable errors have been encountered during the verify MGSTAT0 operation MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 911: Interrupts
The logic used for generating the Flash module interrupts is shown in Figure 26-27. Flash Command Interrupt Request CCIE CCIF DFDIE DFDIF Flash Error Interrupt Request SFDIE SFDIF Figure 26-27. Flash Module Interrupts Implementation MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 912: Wait Mode
26-11) will be changed to unsecure the MCU. Key values of 0x0000 and 0xFFFF are not permitted as backdoor keys. While the Verify Backdoor Access Key command is active, P-Flash memory and EEPROM memory will not be available for read access and will return invalid data. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 913: Unsecuring The Mcu In Special Single Chip Mode Using Bdm
Flash security byte may be programmed to the unsecure state by continuing with the following steps: 7. Send BDM commands to execute the Program P-Flash command write sequence to program the Flash security byte to the unsecured state MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 914: Mode And Security Effects On Flash Command Availability
CCIF high which enables user commands. If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 915: Chapter 27 64 Kbyte Flash Module (S12Ftmrg64K1V1)
The Flash memory may be read as bytes and aligned words. Read access time is one bus cycle for bytes and aligned words. For misaligned words access, the CPU has to perform twice the byte read access command. For Flash memory, an erased bit reads 1 and a programmed bit reads 0. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 916: Glossary
512 bytes • Single bit fault correction and double bit fault detection within a 32-bit double word during read operations • Automated program and erase algorithm with verify and generation of ECC parity bits MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 917: Block Diagram
Interrupt generation on Flash command completion and Flash error detection • Security mechanism to prevent unauthorized access to the Flash memory 27.1.3 Block Diagram The block diagram of the Flash module is shown in Figure 27-1. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 918: External Signal Description
Security Clock Clock Divider FCLK Memory Controller EEPROM 1Kx22 sector 0 sector 1 sector 511 Figure 27-1. FTMRG64K1 Block Diagram 27.2 External Signal Description The Flash module contains no signals that connect off-chip. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 919: Memory Map And Registers
27-3.The P-Flash memory map is shown in Figure 27-2. Table 27-3. P-Flash Memory Addressing Size Global Address Description (Bytes) P-Flash Block 0x3_0000 – 0x3_FFFF 64 K Contains Flash Configuration Field (see Table 27-4) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 920 Section 27.3.2.2, “Flash Security Register (FSEC)” 0x3FF08-0x3_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0x3_FF08 - 0x3_FF0B reserved field should be programmed to 0xFF. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 921 0x0_4008 – 0x0_40B5 Reserved 0x0_40B6 – 0x0_40B7 Version ID 0x0_40B8 – 0x0_40BF Reserved Program Once Field 0x0_40C0 – 0x0_40FF Refer to Section 27.4.6.6, “Program Once Command” Used to track firmware patch versions, see Section 27.4.2 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 922: Register Descriptions
The Flash module contains a set of 20 control and status registers located between Flash module base + 0x0000 and 0x0013. In the case of the writable registers, the write accesses are forbidden during Fash command execution (for more detail, see Caution note in Section 27.3). MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 923 DPS4 DPS3 DPS2 DPS1 DPS0 EEPROT 0x000A CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 FCCOBHI 0x000B CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 FCCOBLO 0x000C FRSV1 Figure 27-4. FTMRG64K1 Register Summary MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 924 All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times but bit 7 remains unwritable. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 925 10.6 11.6 0x0A 11.6 12.6 0x0B 12.6 13.6 0x0C 13.6 14.6 0x0D 14.6 15.6 0x0E 15.6 16.6 0x0F BUSCLK is Greater Than this value. BUSCLK is Less Than or Equal to this value. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 926 Flash module is unsecured using backdoor key access, the SEC bits are forced to 10. Table 27-10. Flash KEYEN States KEYEN[1:0] Status of Backdoor Key Access DISABLED DISABLED ENABLED DISABLED Preferred KEYEN state to disable backdoor key access. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 927 This Flash register is reserved for factory testing. Offset Module Base + 0x000C Reset = Unimplemented or Reserved Figure 27-8. Flash Reserved0 Register (FRSV0) All bits in the FRSV0 register read 0 and are not writable. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 928 SFDIE interrupt enable in the FERCNFG register is set (see Section 27.3.2.6) 27.3.2.6 Flash Error Configuration Register (FERCNFG) The FERCNFG register enables the Flash error interrupts for the FERSTAT flags. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 929 Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see Section 27.6). CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable but not writable, while remaining bits read 0 and are not writable. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 930 Offset Module Base + 0x0007 DFDIF SFDIF Reset = Unimplemented or Reserved Figure 27-12. Flash Error Status Register (FERSTAT) All flags in the FERSTAT register are readable and only writable to clear the flag. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 931 If a double bit fault is detected while reading the P-Flash phrase containing the P-Flash protection byte during the reset sequence, the FPOPEN bit will be cleared and remaining bits in the FPROT register will be set to leave the P-Flash memory fully protected. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 932 Protected Low Range Protected High Range Protected High and Low Ranges Full P-Flash Memory Protected Unprotected Low Range Unprotected High Range Unprotected High and Low Ranges For range sizes, refer to Table 27-19 Table 27-20. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 933 Flash memory at global address 0x3_FF0C during the reset sequence, it can be changed by the user. The P-Flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 934 Scenario FLASH START 0x3_8000 0x3_FFFF Protected region with size Unprotected region defined by FPLS Protected region Protected region with size not defined by FPLS, FPHS defined by FPHS Figure 27-14. P-Flash Protection Scenarios MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 935 Writes must increase the DPS value and the DPOPEN bit can only be written from 1 (protection disabled) to 0 (protection enabled). If the DPOPEN bit is set, the state of the DPS bits is irrelevant. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 936 0x0_0400 – 0x0_049F 160 bytes 000101 0x0_0400 – 0x0_04BF 192 bytes The Protection Size goes on enlarging in step of 32 bytes, for each DPS value increasing of one. 111111 0x0_0400 – 0x0_0BFF 2,048 bytes MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 937 Section 27.4.6. Table 27-24. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] Byte FCCOB Parameter Fields (NVM Command Mode) FCMD[7:0] defining Flash command 6’h0, Global address [17:16] Global address [15:8] Global address [7:0] MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 938 = Unimplemented or Reserved Figure 27-19. Flash Reserved2 Register (FRSV2) All bits in the FRSV2 register read 0 and are not writable. 27.3.2.14 Flash Reserved3 Register (FRSV3) This Flash register is reserved for factory testing. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 939 F in Figure 27-22. If a double bit fault is detected while reading the P-Flash phrase containing the Flash nonvolatile byte during the reset sequence, all bits in the FOPT register will be set. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 940 = Unimplemented or Reserved Figure 27-24. Flash Reserved6 Register (FRSV6) All bits in the FRSV6 register read 0 and are not writable. 27.3.2.19 Flash Reserved7 Register (FRSV7) This Flash register is reserved for factory testing. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 941: Functional Description
IFR Version ID Word The version ID word is stored in the IFR at address 0x0_40B6. The contents of the word are defined in Table 27-26. Table 27-26. IFR Version ID Fields [15:4] [3:0] Reserved VERNUM MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 942: Internal Nvm Resource (Nvmres)
27.3.2.7) and the CCIF flag should be tested to determine the status of the current command write sequence. If CCIF is 0, the previous command write sequence is still active, a new command write sequence cannot be started, and all writes to the FCCOB register are ignored. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 943 Flash command has completed. Upon completion, the Memory Controller will return CCIF to 1 and the FCCOB register will be used to communicate any results. The flow for a generic command write sequence is shown in Figure 27-26. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 944 More Parameters? Write: FSTAT register (to launch command) Clear CCIF 0x80 Read: FSTAT register Bit Polling for Command Completion CCIF Set? Check EXIT Figure 27-26. Generic Flash Command Write Sequence Flowchart MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 945 P-Flash block and other resources within the Flash module. Table 27-28. P-Flash Commands FCMD Command Function on P-Flash Memory Erase Verify All Verify that all P-Flash (and EEPROM) blocks are erased. 0x01 Blocks MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 946 Table 27-29. EEPROM Commands FCMD Command Function on EEPROM Memory Erase Verify All Verify that all EEPROM (and P-Flash) blocks are erased. 0x01 Blocks 0x02 Erase Verify Block Verify that the EEPROM block is erased. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 947: Allowed Simultaneous P-Flash And Eeprom Operations
‘Set User Margin Level’ or ‘Set Field Margin Level’ with anything but the ‘normal’ level specified. See the Note on margin settings in Section 27.4.6.12 Section 27.4.6.13. The ‘Mass Erase’ operations are commands ‘Erase All Blocks’ and ‘Erase Flash Block’ MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 948: Flash Command Description
MGSTAT1 Set if any errors have been encountered during the reador if blank check failed . Set if any non-correctable errors have been encountered during the read or if MGSTAT0 blank check failed. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 949 The Erase Verify P-Flash Section command will verify that a section of code in the P-Flash memory is erased. The Erase Verify P-Flash Section command defines the starting point of the code to be verified and the number of phrases. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 950 CCOBIX[2:0] FCCOB Parameters 0x04 Not Required Read Once phrase index (0x0000 - 0x0007) Read Once word 0 value Read Once word 1 value Read Once word 2 value Read Once word 3 value MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 951 Upon clearing CCIF to launch the Program P-Flash command, the Memory Controller will program the data words to the supplied global address and will then proceed to verify the data words read back as expected. The CCIF flag will set after the Program P-Flash operation has completed. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 952 Valid phrase index values for the Program Once command range from 0x0000 to 0x0007. During execution of the Program Once command, any attempt to read addresses within P-Flash will return invalid data. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 953 Set if any non-correctable errors have been encountered during the verify MGSTAT0 operation 27.4.6.8 Erase Flash Block Command The Erase Flash Block operation will erase all addresses in a P-Flash or EEPROM block. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 954 Upon clearing CCIF to launch the Erase P-Flash Sector command, the Memory Controller will erase the selected Flash sector and then verify that it is erased. The CCIF flag will be set after the Erase P-Flash Sector operation has completed. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 955 The Verify Backdoor Access Key command will only execute if it is enabled by the KEYEN bits in the FSEC register (see Table 27-10). The Verify Backdoor Access Key command releases security if user-supplied keys match those stored in the Flash security bytes of the Flash configuration field (see MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 956 The Set User Margin Level command causes the Memory Controller to set the margin level for future read operations of the P-Flash or EEPROM block. Table 27-54. Set User Margin Level Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters Flash block selection code [1:0] . See 0x0D Table 27-34 Margin level setting. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 957 User margin levels can be used to check that Flash memory contents have adequate margin for normal level read operations. If unexpected results are encountered when checking Flash memory contents at user margin levels, a potential loss of information has been detected. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 958 0x0000 Return to Normal Level 0x0001 User Margin-1 Level 0x0002 User Margin-0 Level 0x0003 Field Margin-1 Level 0x0004 Field Margin-0 Level Read margin to the erased state Read margin to the programmed state MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 959 EEPROM memory is erased. The CCIF flag will set after the Erase Verify EEPROM Section operation has completed. If the section is not erased, it means blank check failed, both MGSTAT bits will be set. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 960 Memory Controller and be programmed if the area is unprotected. The CCOBIX index value at Program EEPROM command launch determines how many words will be programmed in the EEPROM block. The CCIF flag is set when the operation has completed. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 961 Set if the selected area of the EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation Set if any non-correctable errors have been encountered during the verify MGSTAT0 operation MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 962: Interrupts
The logic used for generating the Flash module interrupts is shown in Figure 27-27. Flash Command Interrupt Request CCIE CCIF DFDIE DFDIF Flash Error Interrupt Request SFDIE SFDIF Figure 27-27. Flash Module Interrupts Implementation MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 963: Wait Mode
27-11) will be changed to unsecure the MCU. Key values of 0x0000 and 0xFFFF are not permitted as backdoor keys. While the Verify Backdoor Access Key command is active, P-Flash memory and EEPROM memory will not be available for read access and will return invalid data. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 964: Unsecuring The Mcu In Special Single Chip Mode Using Bdm
Flash security byte may be programmed to the unsecure state by continuing with the following steps: 7. Send BDM commands to execute the Program P-Flash command write sequence to program the Flash security byte to the unsecured state MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 965: Mode And Security Effects On Flash Command Availability
CCIF high which enables user commands. If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 966 64 KByte Flash Module (S12FTMRG64K1V1) MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 967: Chapter 28 96 Kbyte Flash Module (S12Ftmrg96K1V1)
FCCOB register can be written to with a new command. CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 968: Glossary
Program IFR — Nonvolatile information register located in the P-Flash block that contains the Version ID, and the Program Once field. 28.1.2 Features 28.1.2.1 P-Flash Features • 96 Kbytes of P-Flash memory composed of one 96 Kbyte Flash block divided into 192 sectors of 512 bytes MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 969: Block Diagram
Interrupt generation on Flash command completion and Flash error detection • Security mechanism to prevent unauthorized access to the Flash memory 28.1.3 Block Diagram The block diagram of the Flash module is shown in Figure 28-1. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 970: External Signal Description
Security Clock Clock Divider FCLK Memory Controller EEPROM 1.5Kx22 sector 0 sector 1 sector 767 Figure 28-1. FTMRG96K1 Block Diagram 28.2 External Signal Description The Flash module contains no signals that connect off-chip. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 971: Memory Map And Registers
See NVMRES description in Section 28.4.3 28.3.1 Module Memory Map The S12 architecture places the P-Flash memory between global addresses 0x2_8000 and 0x3_FFFF as shown in Table 28-3.The P-Flash memory map is shown in Figure 28-2. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 972 Section 28.3.2.2, “Flash Security Register (FSEC)” 0x3FF08-0x3_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0x3_FF08 - 0x3_FF0B reserved field should be programmed to 0xFF. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 973 0x0_4008 – 0x0_40B5 Reserved 0x0_40B6 – 0x0_40B7 Version ID 0x0_40B8 – 0x0_40BF Reserved Program Once Field 0x0_40C0 – 0x0_40FF Refer to Section 28.4.6.6, “Program Once Command” Used to track firmware patch versions, see Section 28.4.2 MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 974: Register Descriptions
The Flash module contains a set of 20 control and status registers located between Flash module base + 0x0000 and 0x0013. In the case of the writable registers, the write accesses are forbidden during Fash command execution (for more detail, see Caution note in Section 28.3). MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 975 DPS4 DPS3 DPS2 DPS1 DPS0 EEPROT 0x000A CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 FCCOBHI 0x000B CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 FCCOBLO 0x000C FRSV1 Figure 28-4. FTMRG96K1 Register Summary MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 976 All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times but bit 7 remains unwritable. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 977 10.6 11.6 0x0A 11.6 12.6 0x0B 12.6 13.6 0x0C 13.6 14.6 0x0D 14.6 15.6 0x0E 15.6 16.6 0x0F BUSCLK is Greater Than this value. BUSCLK is Less Than or Equal to this value. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 978 Flash module is unsecured using backdoor key access, the SEC bits are forced to 10. Table 28-10. Flash KEYEN States KEYEN[1:0] Status of Backdoor Key Access DISABLED DISABLED ENABLED DISABLED Preferred KEYEN state to disable backdoor key access. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 979 This Flash register is reserved for factory testing. Offset Module Base + 0x000C Reset = Unimplemented or Reserved Figure 28-8. Flash Reserved0 Register (FRSV0) All bits in the FRSV0 register read 0 and are not writable. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 980 SFDIE interrupt enable in the FERCNFG register is set (see Section 28.3.2.6) 28.3.2.6 Flash Error Configuration Register (FERCNFG) The FERCNFG register enables the Flash error interrupts for the FERSTAT flags. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 981 Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see Section 28.6). CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable but not writable, while remaining bits read 0 and are not writable. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 982 Offset Module Base + 0x0007 DFDIF SFDIF Reset = Unimplemented or Reserved Figure 28-12. Flash Error Status Register (FERSTAT) All flags in the FERSTAT register are readable and only writable to clear the flag. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 983 If a double bit fault is detected while reading the P-Flash phrase containing the P-Flash protection byte during the reset sequence, the FPOPEN bit will be cleared and remaining bits in the FPROT register will be set to leave the P-Flash memory fully protected. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 984 Protected Low Range Protected High Range Protected High and Low Ranges Full P-Flash Memory Protected Unprotected Low Range Unprotected High Range Unprotected High and Low Ranges For range sizes, refer to Table 28-19 Table 28-20. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 985 Flash memory at global address 0x3_FF0C during the reset sequence, it can be changed by the user. The P-Flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 986 Scenario FLASH START 0x3_8000 0x3_FFFF Protected region with size Unprotected region defined by FPLS Protected region Protected region with size not defined by FPLS, FPHS defined by FPHS Figure 28-14. P-Flash Protection Scenarios MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 987 During the reset sequence, fields DPOPEN and DPS of the EEPROT register are loaded with the contents of the EEPROM protection byte in the Flash configuration field at global address 0x3_FF0D located in MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 988 0x0_0400 – 0x0_04BF 192 bytes The Protection Size goes on enlarging in step of 32 bytes, for each DPS value increasing of one. 1011111 - to - 1111111 0x0_0400 – 0x0_0FFF 3,072 bytes MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 989 Section 28.4.6. Table 28-24. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] Byte FCCOB Parameter Fields (NVM Command Mode) FCMD[7:0] defining Flash command 6’h0, Global address [17:16] Global address [15:8] Global address [7:0] MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 990 = Unimplemented or Reserved Figure 28-19. Flash Reserved2 Register (FRSV2) All bits in the FRSV2 register read 0 and are not writable. 28.3.2.14 Flash Reserved3 Register (FRSV3) This Flash register is reserved for factory testing. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 991 F in Figure 28-22. If a double bit fault is detected while reading the P-Flash phrase containing the Flash nonvolatile byte during the reset sequence, all bits in the FOPT register will be set. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 992 = Unimplemented or Reserved Figure 28-24. Flash Reserved6 Register (FRSV6) All bits in the FRSV6 register read 0 and are not writable. 28.3.2.19 Flash Reserved7 Register (FRSV7) This Flash register is reserved for factory testing. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 993: Functional Description
IFR Version ID Word The version ID word is stored in the IFR at address 0x0_40B6. The contents of the word are defined in Table 28-26. Table 28-26. IFR Version ID Fields [15:4] [3:0] Reserved VERNUM MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 994: Internal Nvm Resource (Nvmres)
28.3.2.7) and the CCIF flag should be tested to determine the status of the current command write sequence. If CCIF is 0, the previous command write sequence is still active, a new command write sequence cannot be started, and all writes to the FCCOB register are ignored. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 995 Flash command has completed. Upon completion, the Memory Controller will return CCIF to 1 and the FCCOB register will be used to communicate any results. The flow for a generic command write sequence is shown in Figure 28-26. MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 996 More Parameters? Write: FSTAT register (to launch command) Clear CCIF 0x80 Read: FSTAT register Bit Polling for Command Completion CCIF Set? Check EXIT Figure 28-26. Generic Flash Command Write Sequence Flowchart MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 997 P-Flash block and other resources within the Flash module. Table 28-28. P-Flash Commands FCMD Command Function on P-Flash Memory Erase Verify All Verify that all P-Flash (and EEPROM) blocks are erased. 0x01 Blocks MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors...
Page 998 Table 28-29. EEPROM Commands FCMD Command Function on EEPROM Memory Erase Verify All Verify that all EEPROM (and P-Flash) blocks are erased. 0x01 Blocks 0x02 Erase Verify Block Verify that the EEPROM block is erased. MC9S12G Family Reference Manual Rev.1.27 1000 NXP Semiconductors...
Page 999: Allowed Simultaneous P-Flash And Eeprom Operations
‘Set User Margin Level’ or ‘Set Field Margin Level’ with anything but the ‘normal’ level specified. See the Note on margin settings in Section 28.4.6.12 Section 28.4.6.13. The ‘Mass Erase’ operations are commands ‘Erase All Blocks’ and ‘Erase Flash Block’ MC9S12G Family Reference Manual Rev.1.27 NXP Semiconductors 1001...
Page 1000: Flash Command Description
Set if any errors have been encountered during the read or if blank check failed . Set if any non-correctable errors have been encountered during the read or if MGSTAT0 blank check failed. As found in the memory map for FTMRG96K1. MC9S12G Family Reference Manual Rev.1.27 1002 NXP Semiconductors...

NXP Semiconductors MC9S12G Reference Manual

Device Overview Mc9S12G-Family

Table of Contents

Chapter 1 Device Overview MC9S12G-Family

1.9 System Clock Description

Chapter 2 Port Integration Module (S12GPIMV1)

Chapter 3 5V Analog Comparator (ACMPV1)

Chapter 4 Reference Voltage Attenuator (RVAV1)

Chapter 5 S12G Memory Map Controller (S12GMMCV1)

Chapter 6 Interrupt Module (S12SINTV1)

Chapter 7 Background Debug Module (S12SBDMV1)

Chapter 8 S12S Debug Module (S12SDBGV2)

Chapter 9 Security (S12XS9SECV2)

Chapter 10 S12 Clock, Reset and Power Management Unit (S12CPMU)

Chapter 11 Analog-To-Digital Converter (ADC10B8CV2)

Chapter 12 Analog-To-Digital Converter (ADC12B8CV2)

Chapter 13 Analog-To-Digital Converter (ADC10B12CV2)

Chapter 14 Analog-To-Digital Converter (ADC12B12CV2)

Chapter 15 Analog-To-Digital Converter (ADC10B16CV2)

Chapter 16 Analog-To-Digital Converter (ADC12B16CV2)

Chapter 17 Digital Analog Converter (DAC_8B5V)

Chapter 18 Scalable Controller Area Network (S12MSCANV3)

Chapter 19 Pulse-Width Modulator (S12PWM8B8CV2)

Chapter 20 Serial Communication Interface (S12SCIV5)

Chapter 21 Serial Peripheral Interface (S12SPIV5)

Chapter 22 Timer Module (TIM16B6CV3)

Chapter 23 Timer Module (TIM16B8CV3)

Chapter 24 16 Kbyte Flash Module (S12FTMRG16K1V1)

Chapter 25 32 Kbyte Flash Module (S12FTMRG32K1V1)

Chapter 26 48 Kbyte Flash Module (S12FTMRG48K1V1)

Chapter 27 64 Kbyte Flash Module (S12FTMRG64K1V1)

Chapter 28 96 Kbyte Flash Module (S12FTMRG96K1V1)

Chapter 29 128 Kbyte Flash Module (S12FTMRG128K1V1)

Chapter 30 192 Kbyte Flash Module (S12FTMRG192K2V1)

Chapter 31 240 Kbyte Flash Module (S12FTMRG240K2V1)

Appendix A Electrical Characteristics

Appendix B Detailed Register Address Map

Appendix C Ordering and Shipping Information

Appendix D Package and die Information

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Summary of Contents for NXP Semiconductors MC9S12G