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22.5.6
Additional SCI functions............................................................................................................................... 419
22.5.6.1
22.5.6.2
22.5.6.3
22.5.6.4
23.1
Chip specific programmable delay block..................................................................................................................... 421
23.2
Introduction...................................................................................................................................................................422
23.3
Features......................................................................................................................................................................... 422
23.4
Block diagram...............................................................................................................................................................422
23.5
Mode of operation.........................................................................................................................................................423
23.5.1
Single shot delay mode ................................................................................................................................. 423
23.5.2
Continuous count mode................................................................................................................................. 424
23.6
Memory Map and Register Descriptions...................................................................................................................... 425
23.6.1
PDB Control Register 0 (PDB_CTRL0)........................................................................................................425
23.6.2
PDB Control Register 1 (PDB_CTRL1)........................................................................................................426
23.6.3
PDB0 Comparison Low Register (PDB_CMPL0)........................................................................................ 427
23.6.4
PDB0 Comparison High Register (PDB_CMPH0)....................................................................................... 428
23.6.5
PDB0 Counter High/Low (PDB_CNT0)....................................................................................................... 428
23.6.6
PDB1 Comparison Low Register (PDB_CMPL1)........................................................................................ 429
23.6.7
PDB1 Comparison High Register (PDB_CMPH1)....................................................................................... 429
23.6.8
PDB1 Counter High/Low (PDB_CNT1)....................................................................................................... 430
24.1
Introduction...................................................................................................................................................................431
24.2
Features......................................................................................................................................................................... 431
24.3
Block diagram...............................................................................................................................................................431
24.4
Memory Map and Register Descriptions...................................................................................................................... 432
NXP Semiconductors
8- and 9-bit data modes.............................................................................................................. 419
Loop mode................................................................................................................................. 419
Single-wire operation................................................................................................................. 420
Chapter 23
Programmable Delay Block (PDB)
Chapter 24
Inter-peripheral Crossbar Switch (XBAR)
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
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