Features - NXP Semiconductors MC9S08SU16 Reference Manual

Introduction
The inter-integrated circuit (I
communication between a number of devices.
The interface is designed to operate up to at least 400 kbit/s with maximum bus loading
and timing. The I2C device is capable of operating at higher baud rates, up to a maximum
of clock/20, with reduced bus loading. The maximum communication length and the
number of devices that can be connected are limited by a maximum bus capacitance of
400 pF. The I2C module also complies with the System Management Bus (SMBus)
Specification, version 2.

21.2.1 Features

The I2C module has the following features:
• Compatible with The I
• Multimaster operation
• Software programmable for one of 64 different serial clock frequencies
• Software-selectable acknowledge bit
• Interrupt-driven byte-by-byte data transfer
• Arbitration-lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• START and STOP signal generation and detection
• Repeated START signal generation and detection
• Acknowledge bit generation and detection
• Bus busy detection
• General call recognition
• 10-bit address extension
• Support for System Management Bus (SMBus) Specification, version 2
• Low power mode wakeup on slave address match
• Range slave address support
• Double buffering support to achieve higher baud rate
21.2.2 Modes of operation
The I2C module's operation in various low power modes is as follows:
• Run mode: This is the basic mode of operation. To conserve power in this mode,
disable the module.
362
2
C, I2C, or IIC) module provides a method of
2
C-Bus Specification
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
NXP Semiconductors