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Memory map and register definition
Field
0
Reset not caused by POR.
1
POR caused reset.
6
External Reset Pin
PIN
Reset was caused by an active low level on the external reset pin.
0
Reset not caused by external reset pin.
1
Reset came from external reset pin.
5
Windowed COP
WCOP
Reset was caused by the WCOP timer timing out. This reset source may be blocked by
SIM_SOPT1[COPT] =00.
0
Reset not caused by WCOP timeout.
1
Reset caused by WCOP timeout.
4
Illegal Opcode
ILOP
Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP instruction is
considered illegal if stop is disabled by SIM_SOPT1[STOPE] = 0. The BGND instruction is considered
illegal if active background mode is disabled by BDC_SCR[ENBDM] = 0.
0
Reset not caused by an illegal opcode.
1
Reset caused by an illegal opcode.
3
Illegal Address
ILAD
Reset was caused by an attempt to access a illegal address. The illegal address is captured in illegal
address register (ILLAH:ILLAL).
0
Reset not caused by an illegal address.
1
Reset caused by an illegal address.
2
Internal Clock Source Module Reset
LOC
Reset was caused by an ICS module reset.
0
Reset not caused by ICS module.
1
Reset caused by ICS module.
1
Low Voltage Detect
LVD
This bit is set by POR.
NOTE: This bit reset to 1 on POR and LVR and reset to 0 on other reset.
0
Reset not caused by LVD trip or POR.
1
Reset caused by LVD trip or POR.
0
Flash Illegal Access
FILA
Reset was caused by an flash illegal access.
0
Reset not caused by an flash illegal access.
1
Reset caused by flash illegal access.
106
SIM_SRS field descriptions (continued)
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
NXP Semiconductors
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