Power Control - NXP Semiconductors MC9S08SU16 Reference Manual

When a conversion is aborted, the contents of the data register, ADC_R, are not altered.
However, they continue to be the values transferred after the completion of the last
successful conversion. If the conversion was aborted by a reset, ADC_R return to their
reset states.

17.5.3.4 Power control

The ADC module remains in its idle state until a conversion is initiated. If ADACK is
selected as the conversion clock source, the ADACK clock generator is also enabled.
Power consumption when active can be reduced by setting ADC_SC3[ADLPC]. This
results in a lower maximum value for f
17.5.3.5 Sample time and total conversion time
The total conversion time depends on the sample time (as determined by
ADC_SC3[ADLSMP]), the MCU bus frequency, the conversion mode (8-bit, 10-bit or
12-bit), and the frequency of the conversion clock (f
active, sampling of the input begins.ADC_SC3[ADLSMP] selects between short (3.5
ADCK cycles) and long (23.5 ADCK cycles) sample times. When sampling is complete,
the converter is isolated from the input channel and a successive approximation algorithm
is performed to determine the digital value of the analog signal. The result of the
conversion is transferred to ADC_R upon completion of the conversion algorithm.
If the bus frequency is less than the f
conversions cannot be guaranteed when short sample is enabled (ADC_SC3[ADLSMP]
= 0). If the bus frequency is less than 1/11th of the f
for continuous conversions cannot be guaranteed when long sample is enabled
(ADC_SC3[ADLSMP] = 1).
The maximum total conversion time for different conditions is summarized in the table
below.
Table 17-5. Total conversion time vs. control conditions
Conversion type
Single or first continuous 8-bit
Single or first continuous 10-bit or 12-bit
Single or first continuous 8-bit
Single or first continuous 10-bit or 12-bit
Single or first continuous 8-bit
Single or first continuous 10-bit or 12-bit
NXP Semiconductors
(see the data sheet).
ADCK
frequency, precise sample time for continuous
ADCK
ADICLK
0x, 10
0x, 10
0x, 10
0x, 10
11
11
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 17 Analog-to-digital converter (ADC)
). After the module becomes
ADCK
frequency, precise sample time
ADCK
ADLSMP Max total conversion time
0 20 ADCK cycles + 5 bus clock cycles
0 23 ADCK cycles + 5 bus clock cycles
1 40 ADCK cycles + 5 bus clock cycles
1 43 ADCK cycles + 5 bus clock cycles
0 5 µs + 20 ADCK + 5 bus clock cycles
0 5 µs + 23 ADCK + 5 bus clock cycles
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