Pdb0 Comparison Low Register (Pdb_Cmpl0) - NXP Semiconductors MC9S08SU16 Reference Manual

Field
7 PDB1 Counter Selection
CNTSEL1
0 Read the low byte of 16-bit counter of PDB1 via register CNT1
1 Read the high byte of 16-bit counter of PDB1 via register CNT1
6 PDB0 Counter Selection
CNTSEL0
0 Read the low byte of 16-bit counter of PDB0 via register CNT0
1 Read the high byte of 16-bit counter of PDB0 via register CNT0
5–4 Clock Prescaler Selection
PRESCALER
00 Counter uses peripheral clock.
01 Counter uses peripheral clock / 2.
10 Counter uses peripheral clock / 4.
11 Counter uses peripheral clock / 8.
3 PDB1 Software Clear
SWCLR1
Writing a one to this field triggers a reset and stops the counter, and clear output to low. This bit reads as
zero when pdb1 is disabled and reads one when pdb1 is enabled.
2 PDB1 Software Trigger
SWTRG1
When the module is enabled, writing a one to this field generates a soft trigger to PDB1. This bit read is
PDB1 output state in logic level output.
1 PDB0 Software Clear
SWCLR0
Writing a one to this field triggers a reset and stops the counter, and clear output to low. This bit reads as
zero when pdb0 is disabled and reads one when pdb0 is enabled.
0 PDB0 Software Trigger
SWTRG0
When the module is enabled, writing a one to this field generates a soft trigger to PDB0. This bit read is
PDB0 output state in logic level output.

23.6.3 PDB0 Comparison Low Register (PDB_CMPL0)

The Comparison registers contain the high and low bytes of the comparison value for the
counter. After the counter reaches the comparison value, the timer comparison flag
(TCF0) becomes set at the next clock.
Writing to the CMPx0 registers would take effect immediately.
Address: 60h base + 2h offset = 62h
Bit 7
Read
Write
Reset 1
NXP Semiconductors
PDB_CTRL1 field descriptions
NOTE
6 5
1 1
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 23 Programmable Delay Block (PDB)
Description
4 3
CMPL0
1 1
2 1
1 1
0
1
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