Power Modes Behaviors - NXP Semiconductors MC9S08SU16 Reference Manual

clocks to the background debug logic remain active when the MCU enters stop mode, so
background debug communication is still possible. In addition, the voltage regulator does
not enter its low-power standby state but maintains full internal regulation.
Most background commands are not available in stop mode. The memory-access-with-
status commands do not allow memory access, but they report an error indicating that the
MCU is in either stop or wait mode. The BACKGROUND command can be used to
wake the MCU from stop and enter active background mode if the BDC_SCR[ENBDM]
bit is set. After entering background debug mode, all background commands are
available.

6.2.5 Power modes behaviors

Executing the WAIT or STOP command puts the MCU in a low power consumption
mode for standby situations. The system integration module (SIM) holds the CPU in a
non-clocked state. The operation of each of these modes is described in the following
subsections. Both STOP and WAIT clear the
following table shows the low power mode behaviors.
Mode
PMC
ICS
LPO
CPU
Flash
RAM
ADC
CMP
I/O
SCI / I2C
FTM / PWT / PWM / MTIM
WCOP
DBG
IPC
LVD
GDU
PDB
NXP Semiconductors
Table 6-1. Low power mode behavior
Run
Full regulation
On
On
On
On
On
On
On
On
On
On
On
On
On
On
On
On
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
CCR [I], allowing interrupt to occur. The
Wait
Full regulation
On
On
Standby
On
Standby
On
On
On
On
On
On
On
On
On
On
On
Chapter 6 Power Management
Stop
Loose regulation
Standby
Optional On
Standby
Standby
Standby
Optional on
Optional on
States held
Standby
Standby
Optional on
Standby
Standby
Standby
Standby
Standby
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