Fault Pin Filter - NXP Semiconductors MC9S08SU16 Reference Manual

Generator loading
DISMAP3 DISMAP 2
Fault 0
Fault 1
Fault 2
Fault 3
PWM Pin
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
For parts with less than four fault pins, the same controls apply.
The unavailable DISMAP field bits should be set to zero. For
example, if fault 3 is not available as an input, set DISMAP3=0.

26.3.9.1 Fault pin filter

Each fault pin has a filter to test for fault conditions. A fault input transition to a high
state is not declared until the input is sampled high on two consecutive PWM operation
clocks. Only then FFLAGn and FPINn are set. The FPINn bit will remain set until the
fault input is detected low on two consecutive PWM operation clocks. Clear FFLAGn by
writing a 1 to the corresponding fault acknowledge (FTACKn) bit. If the FIEn, FAULTn
pin interrupt enable bit is set, the FFLAGn flag generates an interrupt request. The
interrupt request latch remains set until one of the following actions occur:
• Software clears the FFLAGn flag by writing a 1 to the FTACKn bit
• Software clears the FIEn bit by writing a 0 to it
• A reset occurs
502
DISMAP1 DISMAP 0
Figure 26-28. Fault decoder for PWM 0
Table 26-4. Fault mapping
NOTE
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Controlling Register Bits
DISMAP3–DISMAP0
DISMAP7–DISMAP4
DISMAP11–DISMAP8
DISMAP15–DISMAP12
DISMAP19–DISMAP16
DISMAP23–DISMAP20
Disable PWM Pin 0
NXP Semiconductors