Flash Clock Divider Register (Ftmrh_Fclkdiv) - NXP Semiconductors MC9S08SU16 Reference Manual

Absolute
address
(hex)
Flash Common Command Object Register: Low
183B
(FTMRH_FCCOBLO)
183C Flash Option Register (FTMRH_FOPT)

11.4.1 Flash Clock Divider Register (FTMRH_FCLKDIV)

The FCLKDIV register is used to control timed events in program and erase algorithms.
All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-
high and controls the writability of the FDIV field in user mode. In BDM mode, bits 6-0
are writable any number of times but bit 7 remains unwritable.
The FCLKDIV register must not be written while a flash
command is executing (FSTAT[CCIF] = 0)
Address: 1830h base + 0h offset = 1830h
Bit 7
Read FDIVLD
Write
Reset 0
Field
7 Clock Divider Loaded
FDIVLD
0 FCLKDIV register has not been written since the last reset.
1 FCLKDIV register has been written since the last reset.
6 Clock Divider Locked
FDIVLCK
0 FDIV field is open for writing.
1 FDIV value is locked and cannot be changed. After the lock bit is set high, only reset can clear this bit
and restore writability to the FDIV field in user mode.
FDIV Clock Divider Bits
FDIV[5:0] must be set to effectively divide BUSCLK down to 1MHz to control timed events during flash
program and erase algorithms. Refer to the table in the
recommended values of FDIV based on the BUSCLK frequency.
NXP Semiconductors
FTMRH memory map (continued)
Register name
6 5
FDIVLCK
0 0
FTMRH_FCLKDIV field descriptions
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 11 Flash Memory Module (FTMRH)
Width
(in bits)
8
8
NOTE
4 3
FDIV
0 0
Description
Writing the FCLKDIV register
Section/
Access Reset value
R/W 00h 11.4.8/187
R Undefined 11.4.9/187
2 1
0 0
for the
page
0
0
181