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External Signal Description
17.2.2 Block Diagram
This figure provides a block diagram of the ADC module.
Off-chip Source Channels
AD0 to AD7 from External
Pin Inputs or Reserved
Reserved
Temperature Sensor
Internal Bandgap
Reserved
V
REFH
V
REFL
None (Module Disabled)
On-chip Source Channels
ADHWT
ALT CLK
BUS CLK
ADACK
ASYNC
CLOCK
GENERATOR
17.3 External Signal Description
The ADC module supports up to 24 separate analog inputs. It also requires four supply/
reference/ground connections.
260
7
5-bit ch
6
5-bit ch
5
5-bit ch
4
5-bit ch
3
5-bit ch
2
5-bit ch
1
5-bit ch
0
5-bit ch
Input Channel
AD0
FIFO Fulfilled
AD1
AD2
AD6
AD7
AD21-AD8
ADCK
AD22
AD23
AD28-AD24
AD29
AD30
AD31
ADTRG MODE ADLSMP ADLPC ACFGT
CLOCK
DIVIDER
2
ADICLK
ADIV
Figure 17-1. ADC Block Diagram
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
AFDEP
0
12-bit AD result
1
12-bit AD result
2
12-bit AD result
3
12-bit AD result
4
12-bit AD result
5
12-bit AD result
6
12-bit AD result
7
12-bit AD result
Analog Result
FIFO Fulfilled
SAR ADC
CONTROL
COMPARE
SEQUENCER
LOGIC
ADCO
STOP
ACFE
AIEN
Interrupt to CPU
COCO
Compare Value
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