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Address: 1800h base + Ch offset = 180Ch
Bit
7
Read
0
Write
Reset
0
Field
7
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
6
PMC Clock Gate Control
PMC
This bit controls the clock gate to the PMC module.
0
Bus clock to the PMC module is disabled.
1
Bus clock to the PMC module is enabled.
5
DBG Clock Gate Control
DBG
This bit controls the clock gate to the DBG module.
0
Bus clock to the DBG module is disabled.
1
Bus clock to the DBG module is enabled.
4
NVM Clock Gate Control
NVM
This bit controls the clock gate to the NVM module.
0
Bus clock to the NVM module is disabled.
1
Bus clock to the NVM module is enabled.
3
IPC Clock Gate Control
IPC
This bit controls the clock gate to the IPC module.
0
Bus clock to the IPC module is disabled.
1
Bus clock to the IPC module is enabled.
2
CRC Clock Gate Control
CRC
This bit controls the clock gate to the CRC module.
0
Bus clock to the CRC module is disabled.
1
Bus clock to the CRC module is enabled.
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
9.8.13 System Clock Gating Control 2 Register (SIM_SCGC2)
This register contains control bits to enable or disable the bus clock to the CMP0, GDU,
ADC, IRQ, PDB and KBI modules. Gating off the clocks to unused peripherals is used to
reduce the MCU's run and wait currents.
NXP Semiconductors
6
5
PMC
DBG
0
1
SIM_SCGC1 field descriptions
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 9 System Integration Module (SIM)
4
3
NVM
IPC
1
0
Description
2
1
0
CRC
0
0
0
0
117
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