Functional Description - NXP Semiconductors MC9S08SU16 Reference Manual

Functional description

Field
CV Conversion Result[7:0]
17.5 Functional description
The ADC module is disabled during reset or when the ADC_SC1[ADCH] bits are all
high. The module is idle when a conversion has completed and another conversion has
not been initiated. When idle, the module is in its lowest power state.
The ADC can perform an analog-to-digital conversion on any of the software selectable
channels. In 12-bit mode, the selected channel voltage is converted by a successive
approximation algorithm into a 12-bit digital result. In 10-bit mode, the selected channel
voltage is converted by a successive approximation algorithm into a 10-bit digital result.
In 8-bit mode, the selected channel voltage is converted by a successive approximation
algorithm into a 8-bit digital result.
When the conversion is completed, the result is placed in the data registers (ADC_R). In
10-bit mode, the result is rounded to 10 bits and placed in the data registers (ADC_R). In
8-bit mode, the result is rounded to 8 bits and placed in ADC_R. The conversion
complete flag (ADC_SC1[COCO]) is then set and an interrupt is generated if the
conversion complete interrupt has been enabled (ADC_SC1[AIEN] = 1).
The ADC module has the capability of automatically comparing the result of a
conversion with the contents of its compare registers. The compare function is enabled by
setting the ADC_SC2[ACFE] bit and operates with any of the conversion modes and
configurations.
17.5.1 Clock select and divide control
One of four clock sources can be selected as the clock source for the ADC module. This
clock source is then divided by a configurable value to generate the input clock to the
converter (ADCK). The clock is selected from one of the following sources by means of
the ADC_SC3[ADICLK] bits.
• The bus clock, which is equal to the frequency at which software is executed. This is
the default selection following reset.
• The bus clock divided by 2: For higher bus clock rates, this allows a maximum
divide by 16 of the bus clock.
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ADCx_CVL field descriptions
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Description
NXP Semiconductors