System Clock Gating Control 3 Register (Sim_Scgc3) - NXP Semiconductors MC9S08SU16 Reference Manual

Field
0 Bus clock to the PDB module is disabled.
1 Bus clock to the PDB module is enabled.
0 KBI Clock Gate Control
KBI
This bit controls the clock gate to the KBI module.
0 Bus clock to the KBI module is disabled.
1 Bus clock to the KBI module is enabled.

9.8.14 System Clock Gating Control 3 Register (SIM_SCGC3)

This page register contains control bits to enable or disable the bus clock to the I2C,
PWM, MTIM, PWT, SCI and FTM modules. Gating off the clocks to unused peripherals
is used to reduce the MCU's run and wait currents.
User software must disable the peripheral before disabling the
clocks to the peripheral. When clocks are re-enabled to a
peripheral, the peripheral registers need to be re-initialized by
user software.
Address: 1800h base + Eh offset = 180Eh
Bit 7
Read
I2C
Write
Reset 0
Field
7 I2C Clock Gate Control
I2C
This bit controls the clock gate to the I2C module.
0 Bus clock to the I2C module is disabled.
1 Bus clock to the I2C module is enabled.
6 PWM Clock Gate Control
PWM
This bit controls the clock gate to the PWM module.
0 Bus clock to the PWM module is disabled.
1 Bus clock to the PWM module is enabled.
5 MTIM Clock Gate Control
MTIM
This bit controls the clock gate to the MTIM module.
NXP Semiconductors
SIM_SCGC2 field descriptions (continued)
NOTE
6 5
PWM MTIM PWT1
0 0
SIM_SCGC3 field descriptions
Table continues on the next page...
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
Chapter 9 System Integration Module (SIM)
Description
4 3
PWT0 SCI
0 0
Description
2 1
FTM
0 0
0
0
0
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